AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 253

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

BCR50-BCR55
BCR6
BCR7
BCR9
Blanking Interval Speed Settings 79
BLOCK DIAGRAM 4
Block Diagram Low Latency Receive Configura-
tion 83
Block Diagram No SRAM Configuration 82
Board Interface 28
Boundary Scan Circuit 91
Boundary Scan Register 91
BSR Mode Of Operation 91
Buffer Management 60
Buffer Management Unit 3, 59
Buffer Size Tuning 7
Burst FIFO DMA Transfers 57
Burst Write Transfer 46
Bus Acquisition 42, 43
Bus Command and Byte Enables 26
Bus Configuration Registers 145, 212, 217
Bus Configuration Registers (BCRs) 145
Bus Grant 26
Bus Master DMA Transfers 43
Bus Request 27
by Driver Type 24
C
CLK 26
CLK Waveform for 3.3 V Signaling 230
CLK Waveform for 5 V Signaling 230
CLK_FAC Values 166
Clock 26
Clock Interface 31
Clock Timing 222, 225
COL 30
Collision 30
Collision Detect Function 99
Collision Handling 68
CONNECTION DIAGRAM (144 TQFP) 16
CONNECTION DIAGRAM (160 PQFP) 17
Contents 5
Control and Status Registers 112, 208, 215
CRS 30
Crystal 32
LED1 Status 149
Reserved Locations 178
LED2 Status 151
LED3 Status 153
Full-Duplex Control 155
Am79C978
Crystal Oscillator In 32
Crystal Oscillator Out 32
CSR0
CSR1
CSR10
CSR100
CSR11
CSR112
CSR114
CSR116
CSR12
CSR122
CSR124
CSR125
CSR13
CSR14
CSR15
CSR16
CSR17
CSR18
CSR19
CSR2
CSR20
CSR21
CSR22
CSR23
Controller Status and Control Register 112
Initialization Block Address 0 115
Logical Address Filter 2 125
Bus Timeout 141
Logical Address Filter 3 126
Missed Frame Count 142
Receive Collision Count 142
OnNow Power Mode Register 142
Physical Address Register 0 126
Advanced Feature Control 143
Test Register 1 143
MAC Enhanced Configuration Control 144
Physical Address Register 1 126
Physical Address Register 2 126
Mode 127
Initialization Block Address Lower 128
Initialization Block Address Upper 128
Current Receive Buffer Address Lower 128
Current Receive Buffer Address Upper 128
Initialization Block Address 1 115
Current Transmit Buffer Address Lower 129
Current Transmit Buffer Address Upper 129
Next Receive Buffer Address Lower 129
3