AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 131

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

CSR34: Current Transmit Descriptor Address
Lower
Bit
31-16
15-0
CSR35: Current Transmit Descriptor Address
Upper
Bit
31-16
15-0
CSR36: Next Next Receive Descriptor Address
Lower
Bit
31-16
15-0
Name
RES
CXDAL
Name
RES
CXDAU
Name
RES
NNRDAL
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
current transmit descriptor ad-
dress pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
current transmit descriptor ad-
dress pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
next next receive descriptor ad-
dress pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Am79C978
CSR37: Next Next Receive Descriptor Address
Upper
Bit
31-16 RES
15-0
CSR38: Next Next Transmit Descriptor Address
Lower
Bit
31-16 RES
15-0
CSR39: Next Next Transmit Descriptor Address
Upper
Bit
31-16 RES
15-0
CSR40: Current Receive Byte Count
Bit
31-16 RES
Name
NNRDAU
Name
NNXDAL
Name
NNXDAU
Name
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
zeros and read as undefined.
Contains the upper 16 bits of the
next next receive descriptor ad-
dress pointer.
Description
zeros and read as undefined.
next next transmit descriptor ad-
dress pointer.
Description
zeros and read as undefined.
Contains the upper 16 bits of the
next next transmit descriptor ad-
dress pointer.
Description
zeros and read as undefined.
Reserved locations. Written as
Reserved locations. Written as
Contains the lower 16 bits of the
Reserved locations. Written as
Reserved locations. Written as
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