AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 109

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

the host. It is cleared by H_RESET and is not affected
by S_RESET or by setting the STOP bit.
PCI Interrupt Pin Register
Offset 3Dh
This PCI Interrupt Pin register is an 8-bit register that
indicates the interrupt pin that the Am79C978 controller
is using. The value for the Am79C978 Interrupt Pin reg-
ister is 01h, which corresponds to INTA.
The PCI Interrupt Pin register is located at offset 3Dh in
the PCI Configuration Space. It is read only.
PCI MIN_GNT Register
Offset 3Eh
The PCI MIN_GNT register is an 8-bit register that
specifies the minimum length of a burst period that the
Am79C978 device needs to keep up with the network
activity. The length of the burst period is calculated as-
suming a clock rate of 33 MHz. The register value
specifies the time in units of 1/4 s. The PCI MIN_GNT
register is an alias of BCR22, bits 7-0. It is recom-
mended that BCR22 be programmed to a value of
1818h.
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MIN_GNT register is located at offset 3Eh in
the PCI Configuration Space. It is read only.
PCI MAX_LAT Register
Offset 3Fh
The PCI MAX_LAT register is an 8-bit register that spec-
ifies the maximum arbitration latency the Am79C978
controller can sustain without causing problems to the
network activity. The register value specifies the time in
units of 1/4 µs. The MAX_LAT register is an alias of
BCR22, bits 15-8. It is recommended that BCR22 be
programmed to a value of 1818h.
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MAX_LAT register is located at offset 3Fh in
the PCI Configuration Space. It is read only.
PCI Capability Identifier Register
Offset 40h
Bit
7-0
Name
CAP_ID
tifies the linked list item as being
the PCI Power Management reg-
isters. This register has a default
value of 1h.
register is located at offset 40h in
Description
This register, when set to 1, iden-
The PCI Capabilities Identifier
Am79C978
PCI Next Item Pointer Register
Offset 41h
Bit
7-0
PCI Power Management Capabilities Register
(PMC)
Offset 42h
Note: All bits of this register are loaded from the
EEPROM. The register is aliased to BCR36 for testing
purposes.
Bit
15-11 PME_SPT
Name
NXT_ITM_PTR
Name
the PCI Configuration Space. It is
read only.
Description
points to the starting address of
the next capability. The pointer at
this offset is a null pointer, indi-
cating that this is the last capabil-
ity in the linked list of the
capabilities. This register has a
default value of 0h.
located at offset 41h in the PCI
Configuration Space. It is read
only.
Description
cates the power states in which
the function may assert PME. A
value of 0b for any bit indicates
that the function is not capable of
asserting the PME signal while in
that power state.
asserted from D0.
asserted from D1.
asserted from D2.
asserted from D3
asserted from D3
The Next Item Pointer Register
The PCI Next Pointer Register is
PME Support. This 5-bit field indi-
Bit(11) XXXX1b - PME can be
Bit(12) XXX1Xb - PME can be
Bit(13) XX1XXb - PME can be
Bit(14) X1XXXb - PME can be
Bit(15) 1XXXXb - PME can be
PME_SPT is read only.
hot
cold
.
.
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