AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 195

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

TBR16: 10BASE-T INTERRUPT Status and Enable
Register (Register 16)
The Interrupt bits indicate when there is a change in the
Link Status, Duplex Mode, Auto-Negotiation status, or
Speed status. Register 16 contains the interrupt status
Note:
1. All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.
Bit(s)
15:14
7:5
13
12
10
11
9
8
4
3
2
1
0
Auto-Negotiation Change
Duplex Mode Change
Duplex Mode Change
Interrupt Test Enable
Table 74. TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16)
Link Status Change
Link Status Change
Auto-Neg Change
Speed Change
Speed Change
Reserved
Reserved
(Note 1)
Enable
Enable
Enable
Enable
Enable
Global
Global
Name
1 = When this bit is set, setting bits 12:9 of this register
0 = Bits 4:1 are only set if the interrupt condition (if any
1 = Link Status Change enable
0 = This interrupt is masked
1 = Duplex Mode Change enable
0 = This interrupt is masked
1 = Auto-Negotiation Change enable
0 = This interrupt is masked
1 = Speed Change enable
0 = This interrupt is masked
1= Global Interrupt enable
0 = This interrupt is masked
1 = Link Status has changed on a port
0 = No change in Link Status
1 = Duplex Mode has changed on a port
0 = No change in Duplex mode
1 = Auto-Neg status has changed on a port
0 = No change in Auto-Neg status
1 = Speed status has changed on a port
0 = No change
1 = Indicates a change in status of any of the above
interrupts
0 = Indicates no change in Interrupt Status
will cause a condition that will set bits 4:1
accordingly. The effect is to test the register bits with
a forced interrupt condition.
bits in 12:9 are set) occurs.
Am79C978
Description
and interrupt enable bits. The status is always updated
whether or not the interrupt enable bits are set. When
an interrupt occurs, the system will need to read the in-
terrupt register to clear the status bits and determine
the course of action needed. See Table 74.
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
RO,
RO,
RO,
RO,
RO,
RO
RO
LH
LH
LH
LH
LH
H/W or Soft
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
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