AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 126

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

CSR11: Logical Address Filter 3
Bit
31-16
15-0 LADRF[63:48] Logical
CSR12: Physical Address Register 0
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16
15-0
CSR13: Physical Address Register 1
Note: Bits 15-0 in this register are programmable
through the EEPROM.
126
Name
RES
Name
RES
PADR[15:0] Physical
zeros and read as undefined.
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
PADR[15:0]. The contents of this
register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
Reserved locations. Written as
Description
Reserved locations. Written as
This register can also be loaded
Address
Address
Register,
Filter,
Am79C978
Bit
31-16 RES
15-0
CSR14: Physical Address Register 2
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-0
PADR[31:16] Physical
PADR[47:32] Physical
Name
Name
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
zeros and read as undefined.
PADR[31:16]. The contents of
this register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Description
zeros and read as undefined.
PADR[47:32]. The contents of
this register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Reserved locations. Written as
This register can also be loaded
Reserved locations. Written as
This register can also be loaded
Address
Address
Register,
Register,