MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 87

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
LOCKIF
TRACK
SCMIF
LOCK
LVRF
Field
SCM
5
4
3
2
1
0
Low Voltage Reset Flag — If low voltage reset feature is not available (see device specification) LVRF always
reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1. Writing
a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
Lock Status Bit — LOCK reflects the current state of PLL lock condition. This bit is cleared in self clock mode.
Writes have no effect.
0 PLL VCO is not within the desired tolerance of the target frequency.
1 PLL VCO is within the desired tolerance of the target frequency.
Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self clock mode.
Writes have no effect.
0 Acquisition mode status.
1Tracking mode status.
Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE = 1), SCMIF causes an interrupt request.
0 No change in SCM bit.
1 SCM bit has changed.
Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
0 MCU is operating normally with OSCCLK available.
1 MCU is operating in self clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK
running at its minimum frequency f
Table 2-2. CRGFLG Field Descriptions (continued)
MC9S12XDP512 Data Sheet, Rev. 2.21
SCM
.
Description
Chapter 2 Clocks and Reset Generator (S12CRGV6)
87