MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 1010

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.34 Port P Data Register (PTP)
Read: Anytime.
Write: Anytime.
Port P pins 7–0 are associated with the PWM as well as the SPI1. These pins can be used as general
purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
The PWM function takes precedence over the general purpose I/O and the SPI1 function if the associated
PWM channel is enabled. While channels 6-0 are output only if the respective channel is enabled, channel
7 can be PWM output or input if the shutdown feature is enabled. Refer to PWM section for details.
The SPI1 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section
for details.
24.0.5.35 Port P Input Register (PTIP)
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to detect
overload or short circuit conditions on output pins.
1012
Reset
Reset
PWM
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
SPI
W
W
associated pin values.
R
R
1
PWM7
PTIP7
PTP7
—
0
7
7
= Unimplemented or Reserved
PWM6
PTIP6
PTP6
—
0
6
6
Figure 24-37. Port P Input Register (PTIP)
Figure 24-36. Port P Data Register (PTP)
MC9S12XDP512 Data Sheet, Rev. 2.21
PWM5
PTIP5
PTP5
—
0
5
5
PWM4
PTIP4
PTP4
—
0
4
4
PWM3
PTIP3
PTP3
SS1
—
0
3
3
PWM2
PTIP2
SCK1
PTP2
—
0
2
2
Freescale Semiconductor
MOSI1
PWM1
PTIP1
PTP1
—
0
1
1
MISO1
PWM0
PTIP0
PTP0
—
0
0
0