MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 338

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.20
Read: Anytime
Write only used in the flag clearing mechanism for bit 7. Writing a one to bit 7 clears the flag. Writing a
zero will not affect the current status of the bit.
All bits reset to zero.
338
POLF[3:0]
Reset
MCZF
Field
3:0
7
W
R
MCZF
Modulus Counter Underflow Flag — The flag is set when the modulus down-counter reaches 0x0000.
The flag indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing
mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in
Section 7.3.2.6, “Timer System Control Register 1
First Input Capture Polarity Status — These are read only bits. Writes to these bits have no effect.
Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch
has been read.
Each POLFx corresponds to a timer PORTx input.
0 The first input capture has been caused by a falling edge.
1 The first input capture has been caused by a rising edge.
16-Bit Modulus Down-Counter FLAG Register (MCFLG)
0
7
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
Figure 7-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
= Unimplemented or Reserved
0
0
6
MCPR1
0
0
1
1
Table 7-23. Modulus Counter Prescaler Select
Table 7-24. MCFLG Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
MCPR0
(TSCR1)”.
0
1
0
1
NOTE
0
0
4
Description
(TSCR1)”).
Prescaler Division
POLF3
0
3
Section 7.3.2.6, “Timer
16
1
4
8
POLF2
0
2
POLF1
Freescale Semiconductor
0
1
POLF0
0
0