MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 788

MC9S12XDP512CAL

Manufacturer Part Number
MC9S12XDP512CAL
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9S12XDP512CAL

Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
91
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(16-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDP512CAL
Manufacturer:
FREESCALE
Quantity:
1 928
Part Number:
MC9S12XDP512CAL
Manufacturer:
FREESCALE
Quantity:
4
Part Number:
MC9S12XDP512CAL
Manufacturer:
FREESCA
Quantity:
2 246
Part Number:
MC9S12XDP512CAL
Manufacturer:
FREESCALE
Quantity:
4 576
Part Number:
MC9S12XDP512CAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDP512CAL
Manufacturer:
FREESCALE
Quantity:
4 576
Chapter 21 External Bus Interface (S12XEBIV2)
21.3
This section provides a detailed description of all registers accessible in the XEBI.
21.3.1
The registers associated with the XEBI block are shown in
21.3.2
The following sub-sections provide a detailed description of each register and the individual register bits.
All control bits can be written anytime, but this may have no effect on the related function in certain
operating modes. This allows specific configurations to be set up before changing into the target operating
mode.
790
EBICTL0
EBICTL1
Register
Name
Memory Map and Register Definition
Module Memory Map
Register Descriptions
W
W
R
R
Depending on the operating mode an available function may be enabled,
disabled or depend on the control register bit. Reading the register bits will
reflect the status of related function only if the current operating mode
allows user control. Please refer the individual bit descriptions.
EWAITE
ITHRS
Bit 7
= Unimplemented or Reserved
6
0
0
Figure 21-2. XEBI Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
HDBE
5
0
NOTE
ASIZ4
4
0
Figure
ASIZ3
3
0
21-2.
EXSTR2
ASIZ2
2
Freescale Semiconductor
EXSTR1
ASIZ1
1
EXSTR0
ASIZ0
Bit 0

Related parts for MC9S12XDP512CAL