MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 1248

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Appendix A Electrical Characteristics
Table A-9. shows the configuration of the peripherals for run current measurement.
1250
Table A-9. Peripheral Configurations for Run Supply Current Measurements
Peripheral
MSCAN
XGATE
PWM
COP
DBG
ECT
ATD
SCI
SPI
RTI
API
PIT
IIC
MC9S12XDP512 Data Sheet, Rev. 2.21
the module is configured to run from
PIT is enabled, Micro-timer register 0
the peripheral shall be configured to
configured to loop-back mode using
reads the Status and Flag registers
and does some bit manipulation on
covers all the code executed by the
continously transmit data (0x55) at
of CAN’s, SPI’s, SCI’s in sequence
trigger in outside range. The range
continously transmit data (0x55 or
continously transmit data (0x55 or
accumulator and modulus counter
configured to toggle its pins at the
operate at its maximum specified
XGATE runs in an infinite loop , it
0xAA) at the bit rate of 100Kbit/s
XGATE fetches code from RAM,
and 1 loaded with $0F and timer
registers 0 to 3 are loaded with
the RC oscillator clock source.
the module is enabled and the
comparators are configured to
frequency and to continuously
the peripheral is configured to
enabled, RTI Control Register
output compare mode, Pulse
operate in master mode and
convert voltages on all input
configured to master mode,
configured into loop mode,
COP Warchdog Rate 2
channels in sequence.
speed of 57600 baud
(RTICTL) set to $FF
a bit rate of 1Mbit/s
0xAA) at 1Mbit/s
Configuration
$03/07/0F/1F.
rate of 40kHz
enabled.
the data
core.
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Freescale Semiconductor