MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 166

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.1
Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
166
WRAP[2:0]
ATDD47H
ATDD47L
Reset
Register
Field
Name
2–0
W
R
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
0
7
10-BIT
10-BIT
8-BIT
8-BIT
WRAP2
W
= Unimplemented or Reserved
0
0
0
0
1
1
1
1
BIT 7 MSB
BIT 7
Bit 7
0
0
6
0
0
Figure 5-2. ATD Register Summary (Sheet 5 of 5)
Table 5-2. Multi-Channel Wrap Around Coding
Figure 5-3. ATD Control Register 0 (ATDCTL0)
WRAP1
0
0
1
1
0
0
1
1
= Unimplemented or Reserved
Table 5-1. ATDCTL0 Field Descriptions
BIT 6
BIT 6
MC9S12XDP512 Data Sheet, Rev. 2.21
6
0
0
0
0
5
WRAP0
0
1
0
1
0
1
0
1
BIT 5
BIT 5
5
0
0
Multiple Channel Conversions (MULT = 1)
0
0
4
Wrap Around to AN0 after Converting
Description
BIT 4
BIT 4
4
0
0
Table
0
0
3
Reserved
5-2.
BIT 3
BIT 3
AN1
AN2
AN3
AN4
AN5
AN6
AN7
3
0
0
WRAP2
1
2
BIT 2
BIT 2
2
0
0
WRAP1
Freescale Semiconductor
BIT 9 MSB
1
1
BIT 1
BIT 1
1
0
WRAP0
BIT 8
BIT 0
BIT 0
Bit 0
1
0
0