MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 424

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
10.3.2
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
10.3.2.1
The CANCTL0 register provides various control bits of the MSCAN module as described below.
Read: Anytime
424
0x001C–0x001F
0x0018–0x001B
0x0014–0x0017
0x0020–0x002F
0x0030–0x003F
CANIDMR4–7
CANIDAR4–7
CANIDMRx
CANRXFG
CANTXFG
Register
Reset:
Name
W
R
Register Descriptions
MSCAN Control Register 0 (CANCTL0)
RXFRM
The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the
reset state when the initialization mode is active (INITRQ = 1 and
INITAK = 1). This register is writable again as soon as the initialization
mode is exited (INITRQ = 0 and INITAK = 0).
0
7
R
W
R
W
R
W
R
W
R
W
Bit 7
AM7
AM7
AC7
= Unimplemented
RXACT
Figure 10-3. MSCAN Register Summary (continued)
Figure 10-4. MSCAN Control Register 0 (CANCTL0)
0
6
= Unimplemented or Reserved
AM6
AM6
AC6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
See
See
CSWAI
Section 10.3.3, “Programmer’s Model of Message
Section 10.3.3, “Programmer’s Model of Message
0
5
AM5
AM5
AC5
5
NOTE
SYNCH
0
4
AM4
AM4
AC4
4
TIME
3
0
AM3
AM3
AC3
3
WUPE
u = Unaffected
0
2
AM2
AM2
AC2
2
Storage”
Storage”
Freescale Semiconductor
SLPRQ
0
1
AM1
AM1
AC1
1
INITRQ
Bit 0
AM0
AM0
AC0
1
0