MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 611

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

16.5.3
16.5.3.1
Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking
the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake
up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:
An XIRQ request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set.
16.5.3.2
Interrupt request channels which are configured to be handled by the XGATE are capable of waking up the
XGATE. Interrupt request channels handled by the XGATE do not affect the state of the CPU.
Freescale Semiconductor
Processing Levels
•
•
•
If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.
An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCR.
I bit maskable interrupt requests which are configured to be handled by the XGATE are not capable
of waking up the CPU.
Stacked IPL
IPL in CCR
Wake Up from Stop or Wait Mode
CPU Wake Up from Stop or Wait Mode
XGATE Wake Up from Stop or Wait Mode
7
6
5
4
3
2
1
0
Reset
0
Figure 16-14. Interrupt Processing Example
MC9S12XDP512 Data Sheet, Rev. 2.21
L4
0
4
L7
0
4
7
L1 (Pending)
L3 (Pending)
RTI
0
4
RTI
0
3
Chapter 16 Interrupt (S12XINTV1)
RTI
0
1
RTI
0
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