MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 712

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.11.8 Debug Comparator Data Low Mask Register (DBGXDLM)
Read: Anytime
Write: Anytime when DBG not armed.
19.4
This section provides a complete functional description of the DBG module. If the part is in secure mode,
the DBG module can generate breakpoints but tracing is not possible.
19.4.1
Arming the DBG module by setting ARM in DBGC1 allows triggering, and storing of data in the trace
buffer and can be used to cause breakpoints to the CPU or the XGATE module. The DBG module is made
up of 4 main blocks, the comparators, control logic, the state sequencer and the trace buffer.
The comparators monitor the bus activity of the CPU and XGATE modules. Comparators can be
configured to monitor address and databus. Comparators can also be configured to mask out individual
data bus bits during a compare and to use R/W and word/byte access qualification in the comparison. When
a match with a comparator register value occurs the associated control logic can trigger the state sequencer
to another state
trigger is generated immediately on a comparator match. Using a tagged trigger, at a comparator match,
the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction
queue is a trigger generated. In the case of a transition to final state, bus tracing is triggered and/or a
breakpoint can be generated. Tracing of both CPU and/or XGATE bus activity is possible.
Independent of the state sequencer, a breakpoint can be triggered by the external TAGHI / TAGLO signals,
by an XGATE S/W breakpoint request or by writing to the TRIG bit in the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads.
714
0x002F
Bits [7:0]
Reset
Field
7–0
W
R
Functional Description
DBG Operation
Bit 7
Comparator Data Low Mask Bits — The comparator data low mask bits control whether the selected
comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register
is available only for comparators A and C.
0 Do not compare corresponding data bit
1 Compare corresponding data bit
0
7
(Figure
Figure 19-21. Debug Comparator Data Low Mask Register (DBGXDLM)
19-23). Either forced or tagged triggers are possible. Using a forced trigger, the
6
0
6
Table 19-35. DBGXDLM Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
5
0
5
4
0
4
Description
3
0
3
2
0
2
Freescale Semiconductor
1
0
1
Bit 0
0
0