MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 796

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 21 External Bus Interface (S12XEBIV2)
21.4.2.2.3
21.4.2.3
Depending on the access size and alignment, either a word of read data is made visible on the address lines
or only the related data byte will be presented in the ECLK low phase. For details refer to
21.4.3
All read and write accesses to PRR addresses take two bus clock cycles independent of the operating mode.
If writing to these addresses in emulation modes, the access is directed to both, the internal register and
the external resource while reads will be treated external.
The XEBI control registers also belong to this category.
21.4.4
In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI
supports stretched external bus accesses (wait states).
This feature is available in normal expanded mode and emulation expanded mode for accesses to all
external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2
cycles, respectively.
798
Word read of data at an even and even+1 address
Word read of data at an odd and odd+1 internal RAM address (misaligned)
Byte read of data at an even address
Byte read of data at an odd address
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
R/W
Accesses to Port Replacement Registers
Stretched External Bus Accesses
Internal Visibility Data
Read-Write-Read Access Timing
Table 21-15. Interleaved Read-Write-Read Accesses (1 Cycle)
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Access
addr 0
Table 21-16. IVD Read Data Output
MC9S12XDP512 Data Sheet, Rev. 2.21
high
?
?
1
Access #0
1
iqstat -1
acc 0
low
?
z
z
1
addr 1
data 0
high
z
0
Access #1
2
iqstat 0
acc 1
ivd 0
low
0
(write) data 1
(write) data 1
addr[15:8] (rep.)
ivd(odd+1)
IVD[15:8]
ivd(even)
ivd(even)
addr 2
high
1
Access #2
Freescale Semiconductor
3
iqstat 1
acc 2
low
Table
addr[7:0] (rep.)
1
x
z
z
ivd(even+1)
IVD[7:0]
ivd(odd)
ivd(odd)
21-16.
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