MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 130

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.1
Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
130
WRAP[3:0]
0x0010–0x002F
Reset
Field
ATDDIEN1
PORTAD0
PORTAD1
Register
3:0
0x000D
0x000E
0x000F
Name
W
R
ATDDRxH–
ATDDRxL
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
0
7
W
W
W
W
W
R
R
R
R BIT 9 MSB
R
BIT 7 MSB
= Unimplemented or Reserved
PTAD15
PTAD7
BIT 1
Bit 7
IEN7
u
0
0
6
Figure 4-2. ATD Register Summary (continued)
Figure 4-3. ATD Control Register 0 (ATDCTL0)
= Unimplemented or Reserved
PTAD14
PTAD6
BIT 8
BIT 6
BIT 0
IEN6
Table 4-2. ATDCTL0 Field Descriptions
6
u
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
PTAD13
PTAD5
BIT 7
BIT 5
IEN5
5
0
0
0
0
4
Description
PTAD12
PTAD4
BIT 6
BIT 4
IEN4
4
0
0
WRAP3
Table
1
3
PTAD11
4-3.
PTAD3
BIT 5
BIT 3
IEN3
3
0
0
WRAP2
u = Unaffected
1
2
PTAD10
PTAD2
BIT 4
BIT 2
IEN2
2
0
0
WRAP1
Freescale Semiconductor
PTAD9
PTAD1
1
1
BIT 3
BIT 1
IEN1
1
0
0
WRAP0
PTAD8
PTAD0
BIT 2
BIT 0
IEN0
Bit 0
1
0
0
0