MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 669

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

18.3.2.10 RAM XGATE Upper Boundary Register (RAMXGU)
Read: Anytime
Write: Anytime when RWPE = 0
18.3.2.11 RAM Shared Region Lower Boundary Register (RAMSHL)
Read: Anytime
Write: Anytime when RWPE = 0
Freescale Semiconductor
Address: 0x011D
Address: 0x011E
XGU[6:0]
SHL[6:0]
Reset
Reset
Field
Field
6–0
6–0
W
W
R
R
XGATE Region Upper Boundary Bits 6-0 — These bits define the upper boundary of the RAM region allocated
to the XGATE module in multiples of 256 bytes. The 256 byte block selected by this register is included in the
region. See
RAM Shared Region Lower Boundary Bits 6–0 — These bits define the lower boundary of the shared memory
region in multiples of 256 bytes. The block selected by this register is included in the region. See
for details.
1
1
1
1
7
7
Figure 18-19. RAM Shared Region Lower Boundary Register (RAMSHL)
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 18-18. RAM XGATE Upper Boundary Register (RAMXGU)
Figure 18-25
XGU6
SHL6
1
1
6
6
Table 18-16. RAMXGU Field Descriptions
Table 18-17. RAMSHL Field Descriptions
for details.
MC9S12XDP512 Data Sheet, Rev. 2.21
XGU5
SHL5
1
1
5
5
XGU4
SHL4
1
1
4
4
Description
Description
XGU3
SHL3
1
1
3
3
Chapter 18 Memory Mapping Control (S12XMMCV3)
XGU2
SHL2
1
1
2
2
XGU1
SHL1
1
1
1
1
Figure 18-25
XGU0
SHL0
1
1
0
0
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