MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 667
MC9S12XDP512CAL
Manufacturer Part Number
MC9S12XDP512CAL
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDP512CAL.pdf
(1348 pages)
Specifications of MC9S12XDP512CAL
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
91
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(16-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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18.3.2.8
Read: Anytime
Write: Anytime
These eight index bits are used to page 16 KByte blocks into the Flash page window located in the local
(CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see
accessing up to 4 Mbytes of Flash (in the Global map) within the 64 KByte Local map. The PPAGE age
index register is effectively used to construct paged Flash addresses in the Local map format. The CPU has
special access to read and write this register directly during execution of CALL and RTC instructions. .
Freescale Semiconductor
Address: 0x0030
Reset
W
R
PIX7
Program Page Index Register (PPAGE)
1
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
1
Bit21
PIX6
1
6
Figure 18-15. Program Page Index Register (PPAGE)
PPAGE Register [7:0]
Figure 18-16. PPAGE Address Mapping
MC9S12XDP512 Data Sheet, Rev. 2.21
PIX5
1
5
Global Address [22:0]
CAUTION
Bit14
PIX4
NOTE
1
4
Bit13
PIX3
Address: CPU Local Address
1
3
Chapter 18 Memory Mapping Control (S12XMMCV3)
Address [13:0]
or BDM Local Address
PIX2
1
2
Figure
18-16). This supports
Bit0
PIX1
1
1
PIX0
0
0
667
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