SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 99
SAA7114HV2T
Manufacturer Part Number
SAA7114HV2T
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7114HV2T.pdf
(144 pages)
Specifications of SAA7114HV2T
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Philips Semiconductors
SAA7114_3
Product data sheet
10.2.26 Subaddress 19h
10.2.27 Subaddress 1Fh
Table 64:
Table 65:
Offset
0 LSB
+128 LSB
Bit
D7
D6
D5
D4
D3
D2
D1
D0
128 LSB
Description
status bit for interlace detection
status bit for horizontal and vertical loop
status bit for locked horizontal frequency
identification bit for detected field
frequency
gain value for active luminance channel
is limited; maximum (top)
gain value for active luminance channel
is limited; minimum (bottom)
white peak loop is activated
copy protected source detected
according to Macrovision version up to
7.01
slow time constant active in WIPA mode
ready for capture (all internal loops
locked)
color signal in accordance with selected
standard has been detected
Raw data offset control; RAWO[7:0] 19h[7:0]; see
Status byte video decoder; 1Fh[7:0]; read only register
Control bits D7 to D0
RAWO7 RAWO6 RAWO5 RAWO4 RAWO3 RAWO2 RAWO1 RAWO0
0
1
1
Rev. 03 — 17 January 2006
0
0
1
0
0
1
0
0
1
I
control bit
INTL
HLVLN
HLCK
FIDT
GLIMT
GLIMB
WIPA
COPRO
SLTCA
RDCAP
CODE
2
C-bus
PAL/NTSC/SECAM video decoder
0
0
1
OLDSB
14h[2]
-
0
1
-
-
-
-
0
1
0
1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Figure 19
0
0
1
Value Function
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SAA7114
0
0
1
non-interlaced
interlaced
both loops
locked
unlocked
locked
unlocked
50 Hz
60 Hz
not active
active
not active
active
not active
active
not active
active
not active
active
not active
active
not active
active
0
0
1
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