SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 143

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
25. Contents
1
2
2.1
2.2
2.3
2.4
2.5
2.6
3
4
5
6
7
7.1
7.2
8
8.1
8.1.1
8.1.2
8.1.2.1
8.1.2.2
8.1.3
8.1.3.1
8.1.3.2
8.1.3.3
8.1.4
8.1.5
8.1.6
8.2
8.3
8.3.1
8.3.1.1
8.3.1.2
8.3.1.3
8.3.2
8.3.2.1
8.3.2.2
8.3.3
8.3.3.1
SAA7114_3
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Quick reference data . . . . . . . . . . . . . . . . . . . . . 4
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 14
Video decoder. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
VBI data decoder and slicer . . . . . . . . . . . . . . . 3
Audio clock generation . . . . . . . . . . . . . . . . . . . 3
Digital I/O interfaces . . . . . . . . . . . . . . . . . . . . . 3
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Analog input processing . . . . . . . . . . . . . . . . . 14
Analog control circuits. . . . . . . . . . . . . . . . . . . 14
Clamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chrominance and luminance processing . . . . 19
Chrominance path . . . . . . . . . . . . . . . . . . . . . 20
Luminance path . . . . . . . . . . . . . . . . . . . . . . . 24
Brightness Contrast Saturation (BCS)
control and decoder output levels . . . . . . . . . . 30
Synchronization . . . . . . . . . . . . . . . . . . . . . . . 31
Clock generation circuit . . . . . . . . . . . . . . . . . 31
Power-on reset and CE input . . . . . . . . . . . . . 32
Decoder output formatter . . . . . . . . . . . . . . . . 34
Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Acquisition control and task handling
(subaddresses 80h, 90h, 91h, 94h to 9Fh and
C4h to CFh) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Input field processing . . . . . . . . . . . . . . . . . . . 41
Task handling . . . . . . . . . . . . . . . . . . . . . . . . . 42
Output field processing . . . . . . . . . . . . . . . . . . 43
Horizontal scaling . . . . . . . . . . . . . . . . . . . . . . 45
Horizontal prescaler (subaddresses A0h to
A7h and D0h to D7h) . . . . . . . . . . . . . . . . . . . 45
Horizontal fine scaling (variable phase delay
filter; subaddresses A8h to AFh and D8h
to DFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Vertical scaling . . . . . . . . . . . . . . . . . . . . . . . . 50
Line FIFO buffer (subaddresses 91h, B4h
and C1h, E4h). . . . . . . . . . . . . . . . . . . . . . . . . 50
Rev. 03 — 17 January 2006
8.3.3.2
8.3.3.3
8.4
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.6
8.6.1
8.6.2
8.6.3
9
9.1
9.2
9.3
9.4
9.4.1
9.4.2
9.5
9.6
9.7
9.7.1
9.7.2
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.2.8
10.2.9
10.2.10
10.2.11
Input/output interfaces and ports . . . . . . . . . 64
I
2
C-bus description . . . . . . . . . . . . . . . . . . . . . 76
Vertical scaler (subaddresses B0h to BFh
and E0h to EFh) . . . . . . . . . . . . . . . . . . . . . . . 51
Use of the vertical phase offsets . . . . . . . . . . 52
VBI data decoder and capture
(subaddresses 40h to 7Fh) . . . . . . . . . . . . . . 54
Image port output formatter
(subaddresses 84h to 87h) . . . . . . . . . . . . . . 55
Scaler output formatter
(subaddresses 93h and C3h). . . . . . . . . . . . . 56
Video FIFO (subaddress 86h) . . . . . . . . . . . . 57
Text FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Video and text arbitration (subaddress 86h) . 58
Data stream coding and reference signal
generation (subaddresses 84h, 85h and 93h) 58
Audio clock generation
(subaddresses 30h to 3Fh) . . . . . . . . . . . . . . 61
Master audio clock . . . . . . . . . . . . . . . . . . . . . 61
Signals ASCLK and ALRCLK. . . . . . . . . . . . . 62
Other control signals . . . . . . . . . . . . . . . . . . . 63
Analog terminals . . . . . . . . . . . . . . . . . . . . . . 64
Audio clock signals. . . . . . . . . . . . . . . . . . . . . 64
Clock and real-time synchronization signals . 65
Video expansion port (X port) . . . . . . . . . . . . 66
X port configured as output . . . . . . . . . . . . . . 67
X port configured as input . . . . . . . . . . . . . . . 70
Image port (I port) . . . . . . . . . . . . . . . . . . . . . 70
Host port for 16-bit extension of video data
I/O (H port) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Basic input and output timing diagrams I port
and X port . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I port output timing . . . . . . . . . . . . . . . . . . . . . 73
X port input timing . . . . . . . . . . . . . . . . . . . . . 73
I
I
Subaddress 00h . . . . . . . . . . . . . . . . . . . . . . . 84
Subaddress 01h . . . . . . . . . . . . . . . . . . . . . . . 84
Subaddress 02h . . . . . . . . . . . . . . . . . . . . . . . 84
Subaddress 03h . . . . . . . . . . . . . . . . . . . . . . . 86
Subaddress 04h . . . . . . . . . . . . . . . . . . . . . . . 87
Subaddress 05h . . . . . . . . . . . . . . . . . . . . . . . 87
Subaddress 06h . . . . . . . . . . . . . . . . . . . . . . . 87
Subaddress 07h . . . . . . . . . . . . . . . . . . . . . . . 88
Subaddress 08h . . . . . . . . . . . . . . . . . . . . . . . 88
Subaddress 09h . . . . . . . . . . . . . . . . . . . . . . . 89
Subaddress 0Ah. . . . . . . . . . . . . . . . . . . . . . . 90
2
2
C-bus format . . . . . . . . . . . . . . . . . . . . . . . . 76
C-bus details . . . . . . . . . . . . . . . . . . . . . . . . 84
PAL/NTSC/SECAM video decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SAA7114
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