SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 11

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Table 4:
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[2]
[3]
[4]
[5]
[6]
[7]
SAA7114_3
Product data sheet
Symbol
TEST5
XTRI
XPD7
XPD6
V
XPD5
XPD4
XPD3
XPD2
V
XPD1
XPD0
XRV
XRH
V
XCLK
XDQ
XRDY
TRST
TCK
TMS
V
DDD(ICO5)
SSD(ICO3)
DDD(ICO6)
SSD(EP4)
I = input, O = output, P = power, pu = pull-up.
In accordance with the “IEEE1149.1” standard the pins TDI, TMS, TCK and TRST are input pins with an internal pull-up transistor and
pin TDO is a 3-state output pin.
Pin strapping is done by connecting the pin to the supply via a 3.3 k resistor. During the power-up reset sequence the corresponding
pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down).
Pin RTCO operates as I
address 40h/41h.
Pin ALRCLK = LOW for 24.576 MHz crystal (default); pin ALRCLK = HIGH for 32.110 MHz crystal.
For board design without boundary scan implementation connect the TRST pin to ground.
This pin provides easy initialization of the Boundary Scan Test (BST) circuit. Pin TRST can be used to force the Test Access Port (TAP)
controller to the TEST_LOGIC_RESET state (normal operation) at once.
Pin description
Pin
LQFP100
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
LBGA156
J2
K1
K2
K3
J4
L1
L2
L3
M1
K4
M2
N1
L5
N2
L4
M3
M4
N3
N4
M6
M5
L6
2
C-bus slave address pin; pin RTCO = LOW for slave address 42h/43h (default); pin RTCO = HIGH for slave
…continued
Type
I
I
I/O
I/O
P
I/O
I/O
I/O
I/O
P
I/O
I/O
I/O
I/O
P
I/O
I/O
O
I/pu
I/pu
I/pu
P
[1]
Description
do not connect; reserved for future extensions and for testing: scan input
X port output control signal, affects all X port pins (XPD7 to XPD0, XRH,
XRV, XDQ and XCLK), enable and active polarity is under software control
(bits XPE in subaddress 83h)
MSB of expansion port data
MSB
internal digital core supply voltage 5 (3.3 V)
MSB
MSB
MSB
MSB
internal digital core supply ground 3
MSB
LSB of expansion port data
vertical reference I/O expansion port
horizontal reference I/O expansion port
internal digital core supply voltage 6 (3.3 V)
clock I/O expansion port
data qualifier I/O expansion port
task flag or ready signal from scaler, controlled by bit XRQT
test reset input (active LOW), for boundary scan test
test clock for boundary scan test
test mode select input for boundary scan test or scan test
external digital pad supply ground 4
Rev. 03 — 17 January 2006
1 of expansion port data
2 of expansion port data
3 of expansion port data
4 of expansion port data
5 of expansion port data
6 of expansion port data
[2]
PAL/NTSC/SECAM video decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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SAA7114
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