SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 16

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
SAA7114_3
Product data sheet
8.1.2.1 Clamping
8.1.2.2 Gain control
The clamp control circuit controls the correct clamping of the analog input signals. The
coupling capacitor is also used to store and filter the clamping voltage. An internal digital
clamp comparator generates the information with respect to clamp-up or clamp-down.
The clamping levels for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set with the HCL pulse on the back
porch of the video signal.
The gain control circuit receives (via the I
amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain
Control (AGC) as part of the Analog Input Control (AICO).
The AGC for luminance is used to amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range. The AGC active time is the sync
bottom of the video signal.
Signal (white) peak control limits the gain at signal overshoots. The flow charts
(see
voltage variation within the specified range is automatically eliminated by clamp and
automatic gain control.
Fig 6. Analog line with clamp (HCL) and gain range (HSY)
Fig 7. Automatic gain range
Figure 8
and
Figure
Rev. 03 — 17 January 2006
(1 V (p-p) 18/56 )
9) show more details of the AGC. The influence of supply
511
120
1
analog input level
0 dB
3 dB
6 dB
analog line blanking
maximum
minimum
GAIN
HSY
2
range 9 dB
C-bus) the static gain levels for the two analog
CLAMP
TV line
HCL
PAL/NTSC/SECAM video decoder
ADC input level
mhb325
controlled
mhb726
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
0 dB
SAA7114
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