SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 54

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
SAA7114_3
Product data sheet
8.4 VBI data decoder and capture (subaddresses 40h to 7Fh)
Table 13:
Table 14:
[1]
[2]
[3]
The SAA7114 contains a versatile VBI data decoder.
The implementation and programming model is in accordance with the VBI data slicer
built into the multimedia video data acquisition circuit SAA5284.
The circuitry recovers the actual clock phase during the clock run-in period, slices the data
bits with the selected data rate, and groups them into bytes. The result is buffered into a
dedicated VBI data FIFO with a capacity of 2
frequency, signal source, field frequency and accepted error count must be defined in
subaddress 40h.
Input field under
processing
Upper input lines
Upper input lines
Lower input lines
Lower input lines
Detected input
field ID
0 = upper lines
0 = upper lines
1 = lower lines
1 = lower lines
Case 1: OFIDC[90h[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0
as upper output lines.
Case 2: OFIDC[90h[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as
upper output lines.
Case 3: OFIDC[90h[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as
upper output lines.
Examples for vertical phase offset usage: global equations
Vertical phase offset usage; assignment of the phase offsets
Output field
interpretation
upper output lines UP-UP
lower output lines
upper output lines LO-UP
lower output lines
Task
status
bit
0
1
0
1
Rev. 03 — 17 January 2006
Vertical phase
offset
YPY0[7:0] and
YPC0[7:0]
YPY1[7:0] and
YPC1[7:0]
YPY2[7:0] and
YPC2[7:0]
YPY3[7:0] and
YPC3[7:0]
Used
abbreviation
UP-LO
LO-LO
Case
case 1
case 2
case 3
case 1
case 2
case 3
case 1
case 2
case 3
case 1
case 2
case 3
56 bytes (2
[1]
[2]
[3]
PAL/NTSC/SECAM video decoder
Equation for phase offset
calculation (decimal values)
PHO + 16
PHO
Equation to be used
UP-UP (PHO)
UP-UP
UP-LO
UP-UP (PHO)
UP-LO
UP-UP
LO-LO
LO-UP
LO-LO
LO-LO
LO-LO
LO-UP
PHO
PHO
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
+
+
14 Dwords). The clock
YSCY[15:0]
----------------------------- -
YSCY[15:0]
----------------------------- -
PHO
PHO
64
64
+
+
YSCY[15:0]
----------------------------- - 16
YSCY[15:0]
----------------------------- - 16
SAA7114
+
64
64
16
–
–
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