SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 56

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
SAA7114_3
Product data sheet
8.5.1 Scaler output formatter (subaddresses 93h and C3h)
The clock for the output interface can be derived from an internal clock, decoder,
expansion port, or an externally provided clock which is appropriate for e.g. VGA and
frame buffer. The clock can be up to 33 MHz. The scaler provides the following video
related timing reference events (signals), which are available on pins as defined by
subaddresses 84h and 85h:
The discontinuous data stream at the scaler output is accompanied by a data valid flag (or
data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the
I port data bus (including the HPD pins in 16-bit output mode) are marked with code 00h.
The output interface also arbitrates the transfer between scaled video data and sliced text
data over the I port output.
The bits VITX1 and VITX0 (subaddress 86h) are used to control the arbitration.
As a further operation the serialization of the internal 32-bit Dwords to 8-bit or optional
16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV for video
data, ANC or SAV/EAV codes for sliced text data) are done here.
For handshake with the VGA controller, or other memory or bus interface circuitry,
programmable FIFO flags are provided; see
The output formatter organizes the packing into the output FIFO. The following formats
are available: Y-C
Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93h[2:0], FOI[1:0]
93h[4:3] and FYSK[93h[5]].
The data formats are defined on Dwords, or multiples, and are similar to the video formats
as recommended for PCI multimedia applications (compares to SAA7146A), but planar
formats are not supported.
FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines how many Y only lines
are expected, before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only
lines will be skipped, and the output will always start with a Y/C line.
Additionally the output formatter limits the amplitude range of the video data (controlled by
ILLV[85h[5]]); see
•
•
•
•
•
•
•
Output field ID
Start and end of vertical active video range
Start and end of active video line
Data qualifier or gated clock
Actually activated programming page (if CONLH is used)
Threshold controlled FIFO filling flags (empty, full and filled)
Sliced data marker
B
Table
-C
R
Rev. 03 — 17 January 2006
4 : 2 : 2, Y-C
18.
B
-C
R
4 : 1 : 1, Y-C
Section
8.5.2.
B
PAL/NTSC/SECAM video decoder
-C
R
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
4 : 2 : 0, Y-C
SAA7114
B
-C
R
4 : 1 : 0 and
56 of 144