SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 100

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
SAA7114_3
Product data sheet
10.3.1 Subaddresses 30h to 32h
10.3.2 Subaddresses 34h to 36h
10.3.3 Subaddress 38h
10.3.4 Subaddress 39h
10.3.5 Subaddress 3Ah
10.3 Programming register audio clock generation
See equations in
Table 66:
Table 67:
Table 68:
Table 69:
Table 70:
Subaddress
30h
31h
32h
Subaddress
34h
35h
36h
Subaddress
38h
Subaddress
39h
Bit
D3
D2
D1
D0
Description
audio PLL modes
audio master clock
vertical reference
ALRCLK phase
ASCLK phase
Audio master clock (AMCLK) cycles per field
Audio master clock (AMCLK) nominal increment
Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK)
Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK)
Audio clock control; 3Ah[3:0]
Control bits D7 to D0
ACPF7
ACPF15 ACPF14 ACPF13 ACPF12 ACPF11 ACPF10 ACPF9
-
Control bits D7 to D0
ACNI7
ACNI15
-
Control bits D7 to D0
-
Control bits D7 to D0
-
Section 8.6
Rev. 03 — 17 January 2006
ACPF6
-
ACNI6
ACNI14
-
-
-
Symbol Value Function
APLL
AMVR
LRPH
SCPH
and examples in
ACPF5
-
ACNI5
ACNI13
ACNI21
SDIV5
LRDIV5
0
1
0
1
0
1
0
1
ACPF4
-
ACNI4
ACNI12
ACNI20
SDIV4
LRDIV4
PLL active, AMCLK is field-locked
PLL open, AMCLK is free-running
vertical reference pulse is taken from internal
decoder
vertical reference is taken from XRV input
(expansion port)
ALRCLK edges triggered by falling edges of
ASCLK
ALRCLK edges triggered by rising edges of
ASCLK
ASCLK edges triggered by falling edges of
AMCLK
ASCLK edges triggered by rising edges of AMCLK
Table 22
ACPF3
-
ACNI3
ACNI11
ACNI19
SDIV3
LRDIV3
PAL/NTSC/SECAM video decoder
and
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Table
ACPF2
-
ACNI2
ACNI10
ACNI18
SDIV2
LRDIV2
23.
SAA7114
ACPF1
ACPF17 ACPF16
ACNI1
ACNI9
ACNI17
SDIV1
LRDIV1
ACPF0
ACPF8
ACNI0
ACNI8
ACNI16
SDIV0
LRDIV0
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