SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 42

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

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Philips Semiconductors
SAA7114_3
Product data sheet
8.3.1.2 Task handling
Table 9:
The task handler controls the switching between the two programming register sets. It is
controlled by subaddresses 90h and C0h. A task is enabled via the global control bits
TEA[80h[4]] and TEB[80h[5]].
The handler is then triggered by events, which can be defined for each register set.
In the event of a programming error the task handling and the complete scaler can be
reset to the initial states by setting the software reset bit SWRST[88h[5]] to logic 0.
Especially if the programming registers, related acquisition window and scale are
reprogrammed while a task is active, a software reset must be performed after
programming.
Contrary to the disabling/enabling of a task, which is evaluated at the end of a running
task, when SWRST is at logic 0 it sets the internal state machines directly to their idle
states.
The start condition for the handler is defined by bits STRC[1:0] 90h[1:0] and means: start
immediately, wait for next V-sync, next FID at logic 0 or next FID at logic 1. The FID is
evaluated, if the vertical and horizontal offsets are reached.
When RPTSK[90h[2]] is at logic 1 the actual running task is repeated (under the defined
trigger conditions), before handing control over to the alternate task.
To support field rate reduction, the handler is also enabled to skip fields (bits FSKP[2:0]
90h[5:3]) before executing the task. A TOGGLE flag is generated (used for the correct
output field processing), which changes state at the beginning of a task, every time a task
is activated; examples are given in
Remarks:
XDV1
92h[5]
0
0
0
•
To activate a task the start condition must be fulfilled and the acquisition
window offsets must be reached.
For example, in case of ‘start immediately’, and two regions are defined for one field,
the offset of the lower region must be greater than (offset + length) of the upper
region, if not, the actual counted H and V position at the end of the upper task is
beyond the programmed offsets and the processing will ‘wait for next V’.
XDV0
92h[4]
1
0
0
Processing trigger and start
XDH
92h[2]
0
0
0
Rev. 03 — 17 January 2006
Description
Internal decoder: The processing triggers at the falling edge of the
V123 pulse [see
earliest with the rising edge of the decoder HREF at line number:
External ITU 656 stream: The processing starts earliest with SAV at
line number 23 (50 Hz system), respectively line 20 (60 Hz system)
(according to ITU 656 count)
4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field)
(decoder count)
2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field)
(decoder count)
Section
Figure 24
8.3.1.3.
(50 Hz) and
PAL/NTSC/SECAM video decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Figure 25
(60 Hz)], and starts
SAA7114
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