SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 9

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Table 4:
SAA7114_3
Product data sheet
Symbol
V
AI12
AI1D
AI11
AGND
AOUT
V
V
V
V
CE
LLC
LLC2
RES
SCL
SDA
V
RTS0
RTS1
RTCO
AMCLK
V
ASCLK
ALRCLK
AMXCLK
ITRDY
V
TEST0
ICLK
IDQ
ITRI
DDA1
DDA0
SSA0
DDD(EP2)
SSD(EP1)
DDD(ICO1)
SSD(ICO1)
DDD(ICO2)
Pin description
Pin
LQFP100
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
LBGA156
-
P11
P12
P13
N10
M10
N11
N12, N13
L9
M13
N14
M14
L14
M12
M11
L12
L11
K13
L10
L13
K12
K11
K14
J13
J12
J14
J11
H13
H12
H14
G14
…continued
Type
P
I
I
I
P
O
P
P
P
P
I/pu
O
O
O
I(/O)
I/O
P
O
O
(I/)O
O
P
O
(I/)O
I
I/pu
P
O
I/O
O
I(/O)
[1]
Description
analog supply voltage for analog inputs AI1n (3.3 V)
analog input 12
differential input for ADC channel 1 (pins AI12 and AI11)
analog input 11
analog ground connection
do not connect; analog test output
analog supply voltage (3.3 V) for internal Clock Generation Circuit (CGC)
ground for internal clock generation circuit
external digital pad supply voltage 2 (3.3 V)
external digital pad supply ground 1
Chip Enable (CE) or reset input (with internal pull-up)
line-locked system clock output (27 MHz nominal)
line-locked
reset output (active LOW)
serial clock input (I
serial data input/output (I
internal digital core supply voltage 1 (3.3 V)
real-time status or sync information, controlled by subaddresses
11h and 12h; see
real-time status or sync information, controlled by subaddresses
11h and 12h; see
real-time control output; contains information about actual system clock
frequency, field rate, odd/even sequence, decoder status, subcarrier
frequency and phase and PAL sequence (see external document “RTC
Functional Description” , available on request); the RTCO pin
via I
audio master clock output, up to 50 % of crystal clock
internal digital core supply ground 1
audio serial clock output
audio left/right clock output; can be strapped
resistor to indicate that the default 24.576 MHz crystal (pin
ALRCLK = LOW; internal pull-down) has been replaced by a 32.110 MHz
crystal (pin ALRCLK = HIGH)
audio master external clock input
target ready input, image port (with internal pull-up)
internal digital core supply voltage 2 (3.3 V)
do not connect; reserved for future extensions and for testing: scan output
clock output signal for image port, or optional asynchronous back-end clock
input
output data qualifier for image port (optional: gated clock output)
image port output control signal; selects all input port pins inclusive ICLK,
enable and active polarity are under software control (bits IPE in
subaddress 87h); output path used for testing: scan output
Rev. 03 — 17 January 2006
2
C-bus bit RTCE; see
1
2
clock output (13.5 MHz nominal)
Section 10.2.18
Section 10.2.18
2
C-bus) with inactive output path
2
C-bus)
Table 58
and
and
PAL/NTSC/SECAM video decoder
Section 10.2.19
Section 10.2.19
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
[3] [5]
to supply via a 3.3 k
SAA7114
[3] [4]
is enabled
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