SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 104

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
SAA7114_3
Product data sheet
10.5.2 Subaddresses 83h to 87h
[1]
Table 82:
[1]
[2]
Table 83:
Table 84:
[1]
I port and scaler back-end clock selection
ICLK output and back-end clock is line-locked clock LLC from
decoder
ICLK output and back-end clock is XCLK from X port
ICLK output is LLC and back-end clock is LLC2 clock
Back-end clock is the ICLK input
IDQ pin carries the data qualifier
IDQ pin carries a gated back-end clock (DQ AND CLK)
IDQ generation only for valid data
IDQ qualifies valid data inside the scaling region and all data
outside the scaling region
Output clock phase control
XCLK default output phase, recommended value
XCLK output inverted
XCLK phase shifted by approximately 3 ns
XCLK output inverted and shifted by approximately 3 ns
X port I/O enable
X port output is disabled by software
X port output is enabled by software
X port output is enabled by pin XTRI at logic 0
X port output is enabled by pin XTRI at logic 1
XRDY output signal is A/B task flag from event handler (A = 1)
XRDY output signal is ready signal from scaler path (XRDY = 1
means the SAA7114 is ready to receive data)
X = don’t care.
X = don’t care.
Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.
X = don’t care.
Global control 1; global set 80h[3:0]
X port I/O enable and output clock phase control; global set 83h[5:4]
X port I/O enable and output clock phase control; global set 83h[2:0]
Rev. 03 — 17 January 2006
[1]
PAL/NTSC/SECAM video decoder
Control bits D3 to D0
ICKS3 ICKS2 ICKS1 ICKS0
X
X
X
X
X
X
0
1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Control bits D5 and D4
XPCK1
0
0
1
1
Control bits D2 to D0
XRQT
X
X
X
X
0
1
X
X
X
X
0
1
X
X
[2]
SAA7114
XPE1
0
0
1
1
X
X
0
0
1
1
X
X
X
X
XPCK0
0
1
0
1
[1]
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XPE0
0
1
0
1
X
X
0
1
0
1
X
X
X
X