SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 52
SAA7114HV2T
Manufacturer Part Number
SAA7114HV2T
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7114HV2T.pdf
(144 pages)
Specifications of SAA7114HV2T
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Philips Semiconductors
SAA7114_3
Product data sheet
Fig 31. Basic problem of interlaced vertical scaling (example: downscale
field 1
8.3.3.3 Use of the vertical phase offsets
unscaled input
scale dependent start offset
As described in
interlaced input sequence. Additionally the interpretation and timing between ITU 656 field
ID and real-time detection by means of the state of H-sync at the falling edge of V-sync
may result in different field ID interpretation.
A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the
interlaced input fields are processed, without regard to the actual scale at the starting
point of operation (see
For correct interlaced processing the vertical scaler must be used with respect to the
interlace properties of the input signal and, if required, for conversion of the field
sequences.
Four events should be considered, they are illustrated in
field 2
Section
field 1
Rev. 03 — 17 January 2006
Figure
8.3.1.3, the scaler processing may run randomly over the
no phase offset
scaled output,
mismatched vertical line distances
31).
field 2
3
5
field 1
)
PAL/NTSC/SECAM video decoder
with phase offset
scaled output,
correct scale dependent position
Figure
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
32.
field 2
SAA7114
mhb547
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