SAA7114HV2T NXP Semiconductors, SAA7114HV2T Datasheet - Page 65

• Manufacturer Part Number: SAA7114HV2T
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
SAA7114_3
Product data sheet
9.3 Clock and real-time synchronization signals
The ratios are programmable; see
Table 26:
[1]
For the generation of the line-locked video (pixel) clock LLC, and of the frame-locked
audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is
built-in for fundamental or third harmonic crystals. The supported crystal frequencies are
32.11 MHz or 24.576 MHz (defined during reset by strapping pin ALRCLK).
Alternatively pin XTALI can be driven from an external single-ended oscillator.
The crystal oscillation can be propagated as a clock to other ICs in the system via
pin XTOUT.
The Line-Locked Clock (LLC) is the double pixel clock of nominal 27 MHz. It is locked to
the selected video input, generating baseband video pixels according to “ITU
recommendation 601” . In order to support interfacing circuits, a direct pixel clock (LLC2) is
also provided.
The pins for line and field timing reference signals are RTCO, RTS1 and RTS0. Various
real-time status information can be selected for the RTS pins. The signals are always
available (output) and reflect the synchronization operation of the decoder part in the
SAA7114. The function of the RTS1 and RTS0 pins can be defined by bits RTSE1[3:0]
12h[7:4] and RTSE0[3:0] 12h[3:0].
Table 27:
Symbol
AMCLK
AMXCLK J12
ASCLK
ALRCLK
Symbol
Crystal oscillator
XTALI
XTALO
Pin numbers for LQFP100 in parenthesis.
Pin
K12
(37)
(41)
K14
(39)
J13
(40)
Pin
P2
(7)
P3
(6)
Audio clock pin description
Clock and real-time synchronization signals
[1]
[1]
I/O
I
O
I/O Description
O
I
O
O
Rev. 03 — 17 January 2006
audio master clock output
external audio master clock
input for the clock division
circuit, can be directly
connected to output
AMCLK for standard
applications
serial audio clock output,
can be synchronized to
rising or falling edge of
AMXCLK
audio channel (left/right)
clock output, can be
synchronized to rising or
falling edge of ASCLK
Description
input for crystal oscillator or reference clock
output of crystal oscillator
Section
8.6.
Bit
ACPF[17:0] 32h[1:0] 31h[7:0] 30h[7:0] and
ACNI[21:0] 36h[5:0] 35h[7:0] 34h[7:0]
-
SDIV[5:0] 38h[5:0] and SCPH[3Ah[0]]
LRDIV[5:0] 39h[5:0] and LRPH[3Ah[1]]
PAL/NTSC/SECAM video decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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