MT48H8M32LFB5-75 IT:H Micron Technology Inc, MT48H8M32LFB5-75 IT:H Datasheet - Page 28

• Manufacturer Part Number: MT48H8M32LFB5-75 IT:H
• Description: DRAM Chip Mobile SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-75 IT:H

• Density: 256 Mb
• Maximum Clock Rate: 133 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 8|6 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Address Bus: 14b
• Access Time (max): 8/6ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

COMMAND INHIBIT
NO OPERATION (NOP)
LOAD MODE REGISTER (LMR)
ACTIVE
Figure 8: ACTIVE Command
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
The COMMAND INHIBIT function prevents new commands from being executed by
the device, regardless of whether the CLK signal is enabled. The device is effectively de-
selected. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to perform a NOP to the selected device
(CS# is LOW). This prevents unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected.
The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-
dress term), BA0, and BA1(see Mode Register (page 40)). The LOAD MODE REGISTER
command can only be issued when all banks are idle and a subsequent executable com-
mand cannot be issued until
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The value on the BA0, BA1 inputs selects the bank, and the address provided
selects the row. This row remains active for accesses until a PRECHARGE command is
issued to that bank. A PRECHARGE command must be issued before opening a differ-
ent row in the same bank.
BA0, BA1
Address
RAS#
CAS#
WE#
CKE
CLK
CS#
HIGH
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Bank address
Row address
t
28
MRD is met.
Don’t Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Commands