MT48H8M32LFB5-75 IT:H Micron Technology Inc, MT48H8M32LFB5-75 IT:H Datasheet
MT48H8M32LFB5-75 IT:H
Specifications of MT48H8M32LFB5-75 IT:H
Related parts for MT48H8M32LFB5-75 IT:H
MT48H8M32LFB5-75 IT:H Summary of contents
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... Operating temperature range – Commercial (0° to +70°C) – Industrial (–40°C to +85°C) • Design revision PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN Products and specifications discussed herein are subject to change by Micron without notice. 256Mb: x16, x32 Mobile SDRAM Table 1: Addressing ...
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... Electrical Specifications .45 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Timing Diagrams .54 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Revision History .75 PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 256Mb: x16, x32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 ©2006 Micron Technology, Inc. All rights reserved. Table of Contents ...
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... List of Figures Figure 1: 256Mb Mobile SDRAM Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 2: 16 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 3: 8 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 4: 54-Ball FBGA (Top View) – 8mm x 9mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 5: 90-Ball VFBGA (Top View) – 8mm x 13mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 6: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 7: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 8: EMR Definition ...
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... Specifications and Conditions (x32 .49 DD Table 15: I – Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 DD7 Table 16: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 256Mb: x16, x32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2006 Micron Technology, Inc. All rights reserved. List of Tables ...
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... Figure 1: 256Mb Mobile SDRAM Part Numbering Example Part Number: MT48H8M32LFB5-75LIT V 1.8V/1.8V General Description The Micron memory containing 268,435,456-bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 col- umns by 16 bits. Each of the x32’ ...
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... The 256Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto refresh mode is provided, along with a power-saving deep power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM offers substantial advances in DRAM operating performance, including the abil- ity to synchronously burst data at a high data rate with automatic column-address gen- ...
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... CS# LOGIC WE# CAS# RAS# EXT MODE REGISTER REFRESH MODE REGISTER COUNTER 14 12 A[11:0], ADDRESS 14 BA[1:0] REGISTER 9 PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ BANK0 ROW- 12 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 4096 LATCH ARRAY & (4096 x 512 x 32) DECODER SENSE AMPLIFIERS 4096 I/O GATING ...
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... Ball Assignments Figure 4: 54-Ball FBGA (Top View) – 8mm x 9mm PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ DQ15 V SS SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 DNU V SS UDQM CLK CKE A12 A11 256Mb: x16, x32 Mobile SDRAM Ball Assignments ...
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... Figure 5: 90-Ball VFBGA (Top View) – 8mm x 13mm PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ DQ26 DQ24 V SS DQ28 V V DDQ SSQ V DQ27 DQ25 SSQ V DQ29 DQ30 SSQ V DQ31 NC DDQ V DQM3 CLK CKE A9 DQM1 DNU NC V DQ8 V DDQ SS V DQ10 DQ9 SSQ V DQ12 ...
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... Rev G 6/09 EN Symbol Type CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal ...
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... B8, B3, C1, D1, E9, L9, M1, N1, P3, P8 A9, E7, J9 A7, F9, L7, R7 A1, E3, J1 A3, F1, L3, R3 – E3, E7, H3, H7 PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN Symbol Type DQ[31:0] I/O Data input/output: Data bus. V Supply DQ power: Provide isolated power to DQ for improved noise DDQ immunity. V Supply DQ ground: Provide isolated ground to DQ for improved noise SSQ immunity ...
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... Wait at least 100µs. During this period NOP or COMMAND INHIBIT commands should be applied. No other command other than NOP or COMMAND INHIBIT is allowed during this period. 4. Preform a PRECHARGE ALL command to place the SDRAM into an all banks idle state. 5. Wait at least be applied. ...
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... There are two mode registers in the component: mode register and extended mode reg- ister (EMR). The mode register is illustrated in Figure 6 on page 14. The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL), an operating mode and a write burst mode, as shown in Figure 6 on page 14 ...
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... Figure 6: Mode Register Definition M14 M13 PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN BA1 BA0 A12 A11 A10 M14 M13 M12 M11 M10 Reserved WB OP Mode Program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. Mode Register Definintion 0 Base mode register ...
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... DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 7 on page 16. Reserved states should not be used as unknown operation or incompatibility with future versions may result. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN Order of Accesses Within a Burst Type = Sequential Type = Interleaved A0 ...
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... The low-power EMR is programmed via the MODE REGISTER SET command and retains the stored information until it is programmed again or the device loses power. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CLK READ ...
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... EMR settings will be retained even after exiting deep power-down mode. Temperature-Compensated Self Refresh (TCSR) On this version of the Mobile SDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device. Therefore recom- mended not to program or use the temperature-compensated self refresh control bits in the extended mode register ...
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... Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs. This value should be set according to the application’s requirements. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 256Mb: x16, x32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... BA[1:0] are reserved.) A[12:0] provide the op-code to be written to the selected mode register. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN ...
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... NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER (LMR) The mode register is loaded via inputs A[12:0] and BA[1:0]. (See “Mode Register” on page 13 ...
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... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command, except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “ ...
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... Deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power to the memory array. Data will not be retained once the device enters deep power-down mode. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ RP) is completed. This is determined explicit PRECHARGE command was 22 256Mb: x16, x32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 9). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be ...
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... Figure 7 on page 16 shows general tim- ing for each possible CL setting. Figure 11: READ Command CLK CKE CS# RAS# CAS# WE# A0–A8 A9, A11 A10 BA0, BA1 PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ RCD (MIN) When 2 < RCD (MIN ACTIVE NOP NOP t RCD (MIN) ...
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... Figure 7 on page 16 shows for CL of two and three; data element either the last of a burst of four or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined architecture. A READ command can be initiated on any clock cycle following a previous READ command ...
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... READ burst, provided that I/O contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...
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... READ-to-WRITE DQM COMMAND ADDRESS Note The READ command may be to any bank, and the WRITE command may be to any bank burst of one is used, then DQM is not required. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ met. Note that part of the row precharge time CLK ...
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... READ-to-WRITE with Extra Clock Cycle DQM COMMAND ADDRESS Note The READ command may be to any bank, and the WRITE command may be to any bank. Figure 16: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CLK READ NOP NOP BANK, COL CLK ...
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... This is shown in Figure 17 for each possible CL; data element the last desired data element of a longer burst. Figure 17: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CLK READ NOP NOP BANK, COL n D OUT ...
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... WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 20 on page 31. Data either the last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipe- lined architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command ...
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... PRE- CHARGE command. An example is shown in Figure 21 on page 32. Data either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ ...
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... Each WRITE command may be to any bank. DQM is LOW. Figure 22: WRITE-to-READ CLK COMMAND ADDRESS Note The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW for illustration. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CLK WRITE WRITE WRITE WRITE ...
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... DQM COMMAND ADDRESS Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Figure 24: Terminating a WRITE Burst COMMAND ADDRESS Note: DQMs are LOW. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CLK CK ≥ 15ns WRITE NOP PRECHARGE BANK BANK all) ...
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... CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no REFRESH operations are performed in this mode. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ RP) after the precharge command is issued. Input A10 CLK CKE ...
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... To exit deep power-down mode, CKE must be asserted HIGH. Upon exit of Deep Power- Down mode, at least 200µs of valid clocks with either NOP or COMMAND INHIBIT com- mands are applied to the command bus, followed by a full Mobile SDRAM initialization sequence, is required. Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “ ...
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... Concurrent Auto Precharge An access command (READ or WRITE second bank while an access command with auto precharge enabled on a first bank is executing is not allowed by SDRAM, unless the SDRAM supports concurrent auto precharge. Micron SDRAM support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined in the “READ with Auto Precharge” ...
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... INTERNAL CLOCK COMMAND ADDRESS Note: For this example greater, and DQM is LOW. Figure 29: READ with Auto Precharge Interrupted by a READ COMMAND BANK n Internal States BANK m ADDRESS Note: DQM is LOW. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ READ NOP NOP BANK, COL n D OUT ...
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... Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 32 on page 39). PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CLK ...
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... ADDRESS Note: DQM is LOW. Figure 32: WRITE with Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS Note: DQM is LOW. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CLK WRITE - AP READ - AP NOP NOP BANK n BANK m Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back ...
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... H H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge (provided that 6 ...
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... Table 7, and according to Table 8 on page 43. Precharging: Row activating: Read w/auto- precharge enabled: Write w/auto- precharge enabled: PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ COMMAND INHIBIT (NOP/Continue previous operation OPERATION (NOP/Continue previous operation ACTIVE (Select and activate row) ...
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... RFC is met, the Mobile SDRAM will be in the all banks idle state. Starts with registration of an LMR command and ends when t has been met. Once MRD is met, the Mobile SDRAM will be in the all banks idle state. Starts with registration of a PRECHARGE ALL command and ends t t when RP is met ...
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... AUTO REFRESH, SELF REFRESH and LMR commands may only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ COMMAND INHIBIT (NOP/Continue previous operation ...
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... WRITE to bank m interrupt the WRITE on bank n when registered. The PRE- CHARGE to bank n will begin after m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 256Mb: x16, x32 Mobile SDRAM met, where WR begins when the WRITE to bank Micron Technology, Inc ...
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... OUT Output low voltage: All inputs: I OUT Input leakage current: Any input 0V ≤ V ≤ V (All other balls not under test = 0V Output leakage current: DQ are disabled; 0V ≤ V Operating temperature T (commercial (industrial) A PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN (1.8V) SS (1.8V DDQ Symbol DDQ –4mA ...
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... ACTIVE-to-READ or WRITE delay Refresh period (8192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 256Mb: x16, x32 Mobile SDRAM -75 Symbol Min Max (3) ...
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... Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LMR command to ACTIVE or REFRESH command Data-out High-Z from PRECHARGE command PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 256Mb: x16, x32 Mobile SDRAM Electrical Specifications Symbol -75 t CCD ...
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... CKE is LOW HIGH LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating current: Burst mode; READ or WRITE; All banks active, half DQs toggling every cycle Auto refresh current: CKE = HIGH; CS# = HIGH Deep power-down PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ (MIN) t RCD met; t ...
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... CKE is LOW HIGH LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating current: Burst mode; READ or WRITE; All banks active, half DQs toggling every cycle Auto refresh current: CKE = HIGH; CS# = HIGH Deep power-down PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ (MIN) t RCD met; t ...
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... Typical Self Refresh Current vs. Temperature 150 Full Array 1/2 Array 125 1/4 Array 1/8 Array 100 1/16 Array -40 -30 -20 PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN Maximum Temperature 85ºC 70ºC 45ºC 15ºC 85ºC 70ºC 45ºC 15ºC 85ºC 70ºC 45ºC 15ºC 85ºC 70ºC 45ºC 15º ...
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... Table 16: Capacitance Note: 2; notes appear on page 52 and 53 Parameter Input capacitance: CLK Input capacitance: All other input-only balls Input/output capacitance: DQs PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 256Mb: x16, x32 Mobile SDRAM Symbol Min Max C 1.5 4 2.0 4 2.0 6.0 IO Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... The I frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ DDQ is dependent on output loading and cycle rates. Specified values are obtained ...
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... Auto precharge mode only. The precharge timing budget ( and 7ns for -8 after the first clock delay, after the last WRITE is executed. For auto pre- charge mode, at least one clock cycle is required during PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ for a pulse width ≤ 3ns, and the pulse width can- overshoot ...
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... High 100µs Power-up: V and DD CLK stable Notes: 1. PRE = PRECHARGE command AUTO REFRESH command; LMR = LOAD MODE REGIS- TER command. 2. Only NOPs or COMMAND INHIBITs may be issued during 3. At least one NOP or COMMAND INHIBIT is required during PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ ...
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... A10 SINGLE BANK BA[1:0] BANK(S) High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks power-down mode Notes: 1. Violating refresh requirements during power-down may result in a loss of data. See Table 11 on page 46. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CKS ( ( ) ...
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... CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM ADDR COLUMN A10 BA[1:0] BANK DQ Notes: 1. For this example and auto precharge is disabled. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ NOP NOP OUT OUT 256Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP NOP ...
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... CMS t CMH COMMAND PRECHARGE DQM ADDR ALL BANKS A10 SINGLE BANK BA[1:0] BANK(S) High-Z DQ Precharge all active banks Notes: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not required. See Table 11 on page 46. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ AUTO ...
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... Figure 38: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM ADDR ALL BANKS A10 SINGLE BANK BA[1:0] BANK(S) High-Z DQ Precharge all active banks PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CKS > t RAS ( ( ) ) ( ( ) ) AUTO NOP REFRESH ( ( ) ) ( ( ) ...
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... ROW ADDR ROW A10 DISABLE AUTO PRECHARGE BA[1:0] BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a manual PRECHARGE. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ READ NOP NOP t CMH COLUMN m BANK OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... COMMAND ACTIVE NOP DQM ROW ADDR ENABLE AUTO PRECHARGE ROW A10 BA[1:0] BANK DQ t RCD t RAS t RC Notes: 1. For this example PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ READ NOP NOP t CMS t CMH COLUMN m BANK OUT 256Mb: x16, x32 Mobile SDRAM Timing Diagrams ...
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... DISABLE AUTO PRECHARGE BA[1:0] BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a manual PRECHARGE. 2. PRECHARGE command not allowed or See Table 11 on page 46. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ NOP 2 NOP 2 READ t CMS t CMH COLUMN m BANK ...
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... A10 BA[1:0] BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a manual PRECHARGE. 2. PRECHARGE command not allowed or See Table 11 on page 46. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ NOP 2 NOP 2 READ t CMS t CMH COLUMN m ENABLE AUTO PRECHARGE ...
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... NOP DQM ROW ADDR ENABLE AUTO PRECHARGE ROW A10 BA[1:0] BANK RCD - bank 0 t RAS - bank bank 0 t RRD Notes: 1. For this example PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ READ NOP ACTIVE t CMS t CMH ROW COLUMN m ROW BANK 0 BANK OUT bank 0 t RCD - bank 4 ...
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... NOP t CMS DQM/ DQML, DQMH Address ROW COLUMN ROW A10 BA[1:0] BANK DQ t RCD Notes: 1. For this examples Page left open; no PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ READ NOP NOP NOP t CMH BANK m+1 OUT OUT t LZ 1024 (x16) locations within same row ...
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... CMH COMMAND ACTIVE NOP DQM ROW ADDR ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE BA[1:0] BANK DQ t RCD Notes: 1. For this example PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ READ NOP NOP t CMS t CMH COLUMN m BANK OUT 256Mb: x16, x32 Mobile SDRAM ...
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... ADDR ROW COLUMN ROW A10 DISABLE AUTO PRECHARGE BANK BA[1: RCD t RAS t RC Notes: 1. For this example and the WRITE burst is followed by a manual PRECHARGE. 2. 15ns is required between <D quency. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ WRITE NOP NOP NOP t CMH BANK ...
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... CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ADDR ROW COLUMN ENABLE AUTO PRECHARGE ROW A10 BANK BA[1: RCD t RAS t RC Notes: 1. For this example PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ WRITE NOP NOP NOP t CMH BANK 256Mb: x16, x32 Mobile SDRAM ...
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... BA[1:0] BANK DQ t RCD t RAS t RC Notes: 1. For this example and the WRITE burst is followed by a manual PRECHARGE. 2. 15ns is required between <D 3. PRECHARGE command not allowed or See Table 11 on page 46. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ NOP 3 NOP 3 WRITE t CMS t CMH COLUMN m ...
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... BA[1:0] BANK DQ t RCD t RAS t RC Notes: 1. For this example and the WRITE burst is followed by a manual PRECHARGE. 2. 15ns is required between <D 3. WRITE command not allowed or See Table 11 on page 46. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ NOP 3 NOP 3 WRITE NOP t CMS t CMH ...
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... COMMAND ACTIVE NOP t CMS DQM ROW COLUMN m ADDR ENABLE AUTO PRECHARGE ROW A10 BA[1:0] BANK 0 BANK RCD - bank 0 t RAS - bank bank 0 t RRD Notes: 1. For this example PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ WRITE NOP ACTIVE NOP t CMH ROW ROW BANK ...
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... ROW A10 BA[1:0] BANK DQ t RCD Notes: 1. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” must be satisfied prior to PRECHARGE command. 3. Page left open; no PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ WRITE NOP NOP t CMH t CMS 1 m COLUMN BANK ...
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... CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ADDR ROW ROW A10 BA[1:0] BANK DQ t RCD Notes: 1. For this example PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ WRITE NOP NOP t CMS t CMH COLUMN m ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... CONDITION. THE PRE- REFLOW DIAMETER IS 0. 0.40 SMD BALL PAD. BALL A9 6.40 3.20 3.20 8.00 ±0.10 Notes: 1. All dimensions are in millimeters. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 0.65 ±0.05 6.40 BALL A1 ID 0.80 TYP BALL A1 4.50 ±0. 9.00 ± 0.10 0.80 TYP C L 4.00 ± ...
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... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 0.65 ±0.05 4 ±0.05 ...
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... Added “BL = 2” to the note under Figure 20 on page 31. • Added “BL = 2” to the note under Figure 22 on page 32. • Changed “(see Figure 23)” to “(see Figure 25)” on page 34. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN specification. OZ Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Added a “Power” section to “Options” on page 1. • Replaced old part numbering table with Figure 1. • Changed the clock rate on -75 and -8 for from 111 to 100 in Table 2. PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN 256Mb: x16, x32 Mobile SDRAM and note Table 11 on page 46 ...
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... Changed “Burst Length = 1” in the I • Added a “Contact factory for availability” note to Figure 6. Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/06 • Initial release PDF:09005aef8219eeeb/Source: 09005aef8219eedd 256mb_x16_sdram_y36m_1.fm - Rev G 6/ CK(2) from 9 tp 10ns for -75 and -8 speed grades, and t HZ(2) from 7/8 to 9ns for -75 and -8 speed grades. ...