MT48H8M32LFB5-75 IT:H Micron Technology Inc, MT48H8M32LFB5-75 IT:H Datasheet - Page 26

• Manufacturer Part Number: MT48H8M32LFB5-75 IT:H
• Description: DRAM Chip Mobile SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-75 IT:H

• Density: 256 Mb
• Maximum Clock Rate: 133 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 8|6 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Address Bus: 14b
• Access Time (max): 8/6ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
Mobile LPSDR devices are quad-bank DRAM that operate at 1.8V and include a synchro-
nous interface. All signals are registered on the positive edge of the clock signal, CLK.
Read and write accesses to the device are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE com-
mand are used to select the bank and row to be accessed (BA0 and BA1 select the bank).
The address bits registered coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
The device provides for programmable READ or WRITE burst lengths. An auto pre-
charge function may be enabled to provide a self-timed row precharge that is initiated
at the end of the burst sequence.
The device uses an internal pipelined architecture that enables changing the column
address on every clock cycle to achieve high-speed, fully random access. Precharging
one bank while accessing one of the other three banks will hide the precharge cycles.
The device is designed to operate in 1.8V memory systems. An auto refresh mode is pro-
vided, along with power-saving, power-down, and deep power-down modes. All inputs
and outputs are LVTTL-compatible.
The device offers substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle dur-
ing a burst access.
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
Functional Description
©2008 Micron Technology, Inc. All rights reserved.