M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 86

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
8.2 CPU Clock and Peripheral Function Clock
8.3 Clock Output Function
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral
functions.
8.2.1 CPU Clock and BCLK
8.2.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fCAN0, fCAN1, fC32)
During single-chip mode, the f8, f32, or fC clock can be output from the CLKOUT pin. Use bits CM01 to
CM00 in the CM0 register to select.
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock
or the PLL clock.
If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit
in the CM0 register and bits CM17 to CM16 in the CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to 0 and
bits CM17 to CM16 to 00b (undivided).
After reset, the main clock divided by 8 provides the CPU clock.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU
clock can be output from the BCLK pin by setting the PM07 bit of PM0 register to 0 (output enabled).
Note that when entering stop mode from high-speed or medium-speed mode, on-chip oscillator mode or
on-chip oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to 1 (main
clock turned off) in low-speed mode, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode).
These are operating clocks for the peripheral functions.
Two of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator
clock by dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial interface.
The f8 and f32 clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the
A/D converter.
The fCANi (i =0, 1) clock is derived from the main clock, PLL clock or on-chip oscillator clock by dividing
them by 1 (undivided), 2, 4, 8, or 16, and is used for the CAN module.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral
function clock turned off during wait mode), or when the MCU is in low power dissipation mode, the fi,
fiSIO, fAD, fCAN0, and fCAN1 clocks are turned off
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used
when the sub clock is on.
NOTE:
1. fCAN0 and fCAN1 clocks stop at “H” in CAN0, 1 sleep mode.
Apr 14, 2006
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8. Clock Generation Circuit