M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 276

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
21.1 Memory Map
Figure 21.1 Flash Memory Block Diagram
The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to
store the MCU operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte
space as the block A.
Figure 21.1 shows the Flash Memory Block Diagram.
The user ROM area is divided into several blocks, each of which can be protected (locked) against
programming or erasure. The user ROM area can be rewritten in CPU rewrite, standard serial I/O mode,
parallel I/O mode, and CAN I/O mode. Block A is enabled for use by setting the PM10 bit in the PM1 register
to 1 (block A enabled. CS2 area at addresses 10000h to 26FFFh).
The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in
parallel I/O mode (refer to 21.1.1 Boot Mode). A program in the boot ROM area is executed after a hardware
reset occurs while an “H ” signal is applied to pins CNVSS and P5_0 and an “L” signal is applied to the P5_5
pin (refer to 21.1.1 Boot Mode). A program in the user ROM area is executed after a hardware reset occurs
while an “L” signal is applied to the CNVSS pin. However, the boot ROM area cannot be read.
21.1.1 Boot Mode
The MCU enters boot mode when a hardware reset occurs while an “H ” signal is applied to pins CNVSS
and P5_0 and an “L ” signal is applied to the P5_5 pin. A program in the boot ROM area is executed.
In boot mode, the FMR05 bit in the FMR0 register selects access to the boot ROM area or the user ROM area.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment.
The boot ROM area can be rewritten in parallel I/O mode only. If given rewrite control program using
erase-write mode (EW0 mode) is written in the boot ROM area, the flash memory can be rewritten
according to the system implemented.
Apr 14, 2006
* Shown here is a block diagram during single-chip mode.
NOTES:
0DFFFFh
0E0000h
0C0000h
0CFFFFh
0D0000h
0FFFFFh
00F000h
00FFFFh
0EFFFFh
0F0000h
1. Block A can be made usable by setting the PM10 bit in the PM1 register to 1 (block A enabled, addresses
2. The boot ROM area can only be rewritten in parallel I/O mode.
3. To specify a block, use an even address in that block.
10000h to 26FFFh for CS2 area).
Block A cannot be erased by the erase all unlocked block command. Use the block erase command to
erase it.
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(32+8+8+8+4+4) Kbytes
Block A: 4 Kbytes
Block 8: 64 Kbytes
Block 7: 64 Kbytes
Block 6: 64 Kbytes
_______
Block 5 to 0
(1)
User ROM area
0F0000h
0F7FFFh
0F8000h
0F9FFFh
0FA000h
0FBFFFh
0FC000h
0FDFFFh
0FE000h
0FEFFFh
0FF000h
0FFFFFh
Block 5: 32 Kbytes
Block 4: 8 Kbytes
Block 3: 8 Kbytes
Block 2: 8 Kbytes
Block 1: 4 Kbytes
Block 0: 4 Kbytes
0FF000h
0FFFFFh
Boot ROM area
4 Kbytes
21. Flash Memory Version
(2)