M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 72
M306N4FGTFP
Manufacturer Part Number
M306N4FGTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N4FGGPU3.pdf
(94 pages)
3.M306N4FGGPU3.pdf
(414 pages)
Specifications of M306N4FGTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 7.8 Software Wait Related Bits and Bus Cycles
NOTES:
SFR
Internal
ROM, RAM
External
area
Area
1.
2. To access in multiplexed bus mode, set the corresponding bit of bits CS0W to CS3W to 0 (with wait state).
3. After reset, the PM17 bit is set to 0 (without wait state), all of bits CS0W to CS3W are set to 0 (with wait
4. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by the
5. When the PM17 bit is set to 1 and access an external area, set the CSiW bits (i = 0 to 3) to 0 (with wait
To use the RDY signal, set this bit to 0.
state), and the CSE register is set to 00h (one wait state for CS0 to CS3). Therefore, the internal RAM
and internal ROM are accessed with no wait state, and all external areas are accessed with one wait
state.
PM20 bit in the PM2 register. When using PLL clock over 16 MHz, be sure to set the PM20 bit to 0
(2 wait cycles).
state).
Apr 14, 2006
Bus Mode
Separate
bus
Multiplexed
bus
-
-
-
-
(2)
________
PM2 Register
PM20 Bit
page 48 of 376
-
-
-
-
-
-
-
-
-
-
-
0
1
PM1 Register
PM17 Bit
-
-
-
-
-
-
-
-
0
1
0
1
1
(5)
CSR Register
CS3W Bit
CS2W Bit
CS1W Bit
CS0W Bit
-
-
-
-
1
0
0
0
0
0
0
0
0
(1)
(1)
(1)
(1)
Bits CS31W to CS30W
Bits CS21W to CS20W
Bits CS11W to CS10W
Bits CS01W to CS00W
CSE Register
00b
00b
01b
10b
00b
00b
01b
10b
00b
-
-
-
-
_______
_______
Software
No wait
No wait
2 waits
3 waits
2 waits
3 waits
1 wait
1 wait
1 wait
1 wait
1 wait
Wait
-
-
3 BCLK cycles
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
1 BCLK cycle (read)
2 BCLK cycles (write)
2 BCLK cycles
3 BCLK cycles
4 BCLK cycles
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
4 BCLK cycles
3 BCLK cycles
Bus Cycle
(3)
(4)
(4)
(3)
7. Bus
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