M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 196

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.25 Detection of Start and Stop Condition
15.1.3.1 Detection of Start and Stop Condition
15.1.3.2 Output of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when
the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Figure 15.25 shows the Detection of Start and Stop Condition.
Because the start and stop condition-detected interrupts share the interrupt control register and vector,
check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt.
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to 1 (start).
A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to 1 (start).
A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to 1 (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to 1 (start).
(2) Set the STSPSEL bit in the UiSMR4 register to 1 (output).
Table 15.13 and Figure 15.26 show the STSPSEL Bit Functions.
Apr 14, 2006
i = 0 to 2
3 to 6 cycles < duration for setting-up
3 to 6 cycles < duration for holding
NOTE:
(Start condition)
(Stop condition)
1.When the PCLK1 bit in the PCLKR register = 1, this is the cycle number
of f1SIO, and when the PCLK1 bit = 0, this is the cycle number of f2SIO.
SDA i
page 172 of 376
SDAi
SCLi
Duration for
setting-up
(1)
(1)
Duration for
holding
15. Serial Interface