M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 175

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 15.1 Clock Synchronous Serial I/O Mode Specifications
i = 0 to 2
NOTES:
Transfer data format
Transfer clock
Transmit/receive control
Transmit start condition
Receive start condition
Interrupt request
generation timing
Error detection
Select function
15.1.1 Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data.
Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers to
be Used in and Setting in Clock Synchronous Serial I/O Mode.
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
2. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register; the U2IRS bit is bit 4 in the U2C1 register.
3. If an overrun error occurs, the receive data of UiRB register will be undefined. The IR bit in the SiRIC register
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
remains unchanged.
Apr 14, 2006
Item
page 151 of 376
Transfer data length: 8 bits
The CKDIR bit in the UiMR register = 0 (internal clock) : fj/(2(n+1))
• fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register
Selectable from CTS function, RTS function or CTS/RTS function disabled
Before transmission can start, meet the following requirements
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
• If CTS function is selected, input on the CTSi pin = L
Before reception can start, meet the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit
• The UiIRS bit =1 (transmission completed): when the serial interface finished
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
• Switching serial data logic
• Transfer clock output from multiple pins selection (UART1)
• Separate CTS/RTS pins (UART0)
The CKDIR bit = 1 (external clock) : Input from CLKi pin
_________
CTS0 and RTS0 are input/output from separate pins
UiTB register to the UARTi transmit register (at start of transmission)
transmitting data from the UARTi transmit register
completion of reception)
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 7th bit of the next data
Whether to start transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected
Reception is enabled immediately by reading the UiRB register
This function reverses the logic value of the transmit/receive data
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
Transfer data input/output can be selected to occur synchronously with the rising or
the falling edge of the transfer clock
_______
_______ _______
_________
(3)
(2)
_______
= 0 (transmit buffer empty): when transferring data from the
_______
Specification
_______
_______ _______
(1)
(1)
15. Serial Interface
00h to FFh