M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 172

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.8 Registers UCON, and U0SMR to U2SMR
UART Transmit/Receive Control Register 2
NOTE:
UARTi Special Mode Register (i = 0 to 2)
NOTES:
b7
b7
1. When using multiple transfer clock output pins, make sure the following conditions are met:
1. The BBS bit is set to 0 by writing 0 in a program (writing 1 has no effect).
2. Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer
3. When a transfer begins, the SSS bit is set to 0 (not synchronized to RXDi).
Apr 14, 2006
b6
b6
A0 in UART2.
The CKDIR bit in the U1MR register = 0 (internal clock)
b5
b5
b4
b4
b3
b3
0
b2
b2
page 148 of 376
b1
b1
b0
b0
CLKMD0
CLKMD1
U0RRM
U1RRM
ABSCS
U0IRS
U1IRS
Symbol
RCSP
Symbol
ACSE
IICM
ABC
BBS
SSS
(b7)
U0SMR to U2SMR
(b3)
(b7)
Bit
Bit
-
-
-
Symbol
Symbol
UCON
UART0 transmit interrupt
source select bit
UART1 transmit interrupt
source select bit
UART0 continuous
receive mode enable bit
UART1 continuous
receive mode enable bit
UART1 CLK/CLKS
select bit 0
UART1 CLK/CLKS
select bit 1
Separate UART0
CTS/RTS bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
I
Arbitration lost detecting
flag control bit
Bus busy flag
Reserved bit
Bus collision detect
sampling clock select bit
Auto clear function
select bit of transmit
enable bit
Transmit start condition
select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
2
C mode select bit
Bit Name
Bit Name
(1)
01EFh, 01F3h, 01F7h
0 : Transmit buffer empty (Tl bit = 1)
1 : Transmission completed (TXEPT bit = 1)
0 : Transmit buffer empty (Tl bit = 1)
1 : Transmission completed (TXEPT bit = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Effective when the CLKMD1 bit = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
0 : CLK output is only CLK1
1 : Transfer clock output from multiple
0 : CTS/RTS shared pin
1 : CTS/RTS separated
0 : Other than I
1 : I
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
Set to 0
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj
0 : No auto clear function
1 : Auto clear at occurrence of bus
0 : Not synchronized to RXDi
1 : Synchronized to RXDi
Address
Address
pins function selected
(CTS0 supplied from the P6_4 pin)
collision
03B0h
2
C mode
Function
Function
2
C mode
After Reset
After Reset
(3)
X0000000b
X0000000b
(2)
15. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
-
-
(1)