M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 407

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.00 Nov. 10, 2004
2.10 Jun. 24, 2005
Rev.
Date
REVISION HISTORY
Page
319
322
323
327
328
330
331
332
217
218
219
222
233
19
53
68
–
2
4
23.9 A/D Converter: last item is added. (When setting the ADST bit to •••)
23.10.2 Performing CAN Configuration is added.
23.10.3 Suggestions to Reduce Power Consumption is added.
23.13 Mask ROM Version is added.
23.14.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation
Mode is revised.
23.15 Flash Memory Programming Using Boot Program is added.
23.16 Noise is added.
Appendix 1. Package Dimensions: 100P6Q-A is added.
Revised edition issued
* The contents of product are revised. (Normal-ver. is added.)
* Revised parts and revised contents are as follows (except for expressional change).
Table 1.1 Performance outline of M16C/6N Group (M16C/6N4)
Table 1.2 Product List is revised. (Normal-ver. is added.)
Figure 1.2 Type No., Memory Size, and Package:
Figure 4.7 SFR Information (7): NOTE 1 is revised.
Figure 8.4 CM2 Register: The value of After Reset is revised.
Figure 8.13 State Transition in Normal Operation Mode: NOTE 7 is revised.
Figure 19.6 C0MCTLj and C1MCTLj Registers
Figure 19.7 C0CTLR and C1CTLR Registers (upper)
Figure 19.7 C0CTLR and C1CTLR Registers (lower)
Figure 19.8 C0STR and C1STR Registers (upper): NOTE 1 is deleted.
Figure 19.8 C0STR and C1STR Registers (lower)
Figure 19.11 C0RECR, C1RECR Registers, C0TECR, C1TECR Registers, C0TSR,
C1TSR Registers, and C0AFS, C1AFS Registers
19.15.1 Reception (1): “(refer to 19.15.2 Transmission)” is deleted.
• Performance outline of Normal-ver. is added.
• "(no): Normal-ver." is added to Characteristics.
• RemActive bit: Function is revised.
• RspLock bit: Bit Name is revised.
• NOTE 2 is revised.
• LoopBack bit: The expression of Function is revised.
• BasicCAN bit: The expression of Function is revised.
• TSPreScale bit: Bit Symbol is revised. (“Bit1, Bit0” is deleted.)
• TSReset bit: The expression of Function is revised.
• RetBusOff bit: The expression of Function is revised.
• RXOnly bit: The expression of Function is revised.
• State_LoopBack bit: The expression of Function is revised.
• State_BasicCAN bit: The expression of Function is revised.
• C0RECR, C1RECR Registers: NOTE 2 is deleted.
• C0TECR, C1TECR Registers: NOTE 1 is deleted.
• C0TSR, C1TSR Registers: NOTE 1 is deleted.
M16C/6N Group (M16C/6N4) Hardware Manual
C-7
Description
Summary