M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 80

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 8.5 PCLKR Register
Figure 8.6 CCLKR Register
NOTE:
Peripheral Clock Select Register
b7
0 0 0
1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
NOTES:
Apr 14, 2006
CAN0/1 Clock Select Register
b6
b7
1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
2. Set only when the Reset bit in the CiCTLR register (i = 0, 1) = 1 (reset/Initialization mode).
3. Before setting this bit to 1, set the Sleep bit in the CiCTLR to 1 (sleep mode enabled).
b6
b5
b5
0
b4
b4
0
b3
b3
0
b2
page 56 of 376
b2
b1
b1
b0
b0
Bit Symbol
Bit Symbol
PCLK0
PCLK1
(b7-b2)
CCLK0
CCLK1
CCLK2
CCLK3
CCLK4
CCLK5
CCLK6
CCLK7
Symbol
PCLKR
-
Symbol
CCLKR
(1)
Timers A, B, and A/D clock
select bit
(Clock source for timers A, B,
SI/O clock select bit
(Clock source for UART0 to UART2,
Reserved bits
(1)
CAN0 clock select bits
CAN0 CPU interface
sleep bit
CAN1 clock select bits
CAN1 CPU interface
sleep bit
SI/O3)
the dead time timer and A/D)
Bit Name
Address
(3)
(3)
025Fh
Bit Name
Address
025Eh
(2)
(2)
After Reset
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
1 0 0: Divide-by-16
1 0 1 :
1 1 0 :
1 1 1 :
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
1 0 0 : Divide-by-16
1 0 1 :
1 1 0 :
1 1 1 :
0: CAN1 CPU interface operating
1: CAN1 CPU interface in sleep
b2 b1 b0
b6 b5 b4
After Reset
00h
00h
0 : Divide-by-2 of fAD, f2
1 : fAD, f1
0 : f2SIO
1 : f1SIO
Set to 0
Do not set a value
Do not set a value
Function
Function
8. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW