M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 394

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
23.15 Flash Memory Version
23.15.1 Functions to Prevent Flash Memory from Rewriting
23.15.2 Stop Mode
23.15.3 Wait Mode
23.15.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode
23.15.5 Writing Command and Data
23.15.6 Program Command
23.15.7 Lock Bit Program Command
23.15.8 Operating Speed
ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and
0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in
standard serial I/O mode and CAN I/O mode.
The ROMCP register is mapped in address 0FFFFFh. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of MCU, these addresses are allocated to the vector addresses (H) of fixed
vectors.
When entering stop mode, execute the instruction which sets the CM10 bit to 1 (stop mode) after setting
the FMR01 bit to 0 (CPU rewrite mode disabled) and disabling the DMA transfer.
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled)
before executing the WAIT instruction.
If the CM05 bit is set to 1 (main clock stopped), do not execute the following commands:
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
• Read lock bit status
Write commands and data to even addresses in the user ROM area.
By writing xx40h in the first bus cycle and data to the write address in the second bus cycle, an
auto-program operation (data program and verify) will start. The address value specified in the first bus
cycle must be the same even address as the write address specified in the second bus cycle.
By writing xx77h in the first bus cycle and xxD0h to the highest-order even address of a block in the
second bus cycle, the lock bit for the specified block is set to 0. The address value specified in the first bus
cycle must be the same highest-order even address of a block specified in the second bus cycle.
Before entering CPU rewrite mode (EW0 or EW1 mode), set the CM11 bit in the CM1 register to 0 (main
clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and bits CM17 to
CM16 in the CM1 register. Also, set the PM17 bit in the PM1 register to 1 (with wait state).
Apr 14, 2006
page 370 of 376
23. Usage Notes