M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 341

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
NOTES:
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85
Table 22.49 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
d(DB-WR)
h(WR-DB)
d(BCLK-HLDA)
Symbol
3. This standard value shows the timing when the
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – V
by a circuit of the right figure.
For example, when V
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 V
Apr 14, 2006
0.5 ✕ 10
f(BCLK)
(n – 0.5) ✕ 10
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
__________
HLDA output delay time
f(BCLK)
9
– 10 [ns]
page 317 of 376
9
– 40 [ns]
OL
OL
/ V
= 0.2 V
CC
Parameter
)
CC
/ V
CC
When n = 1, f(BCLK) is 12.5 MHz or less.
n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
CC
, C = 30 pF,
) = 6.7 ns.
(3)
(3)
°
C unless otherwise specified)
Figure 22.14
Measuring
Condition
22. Electric Characteristics (Normal-ver.)
DBi
(NOTE 1)
(NOTE 2)
(NOTE 1)
Min.
–4
4
0
4
0
0
4
Standard
C
R
Max.
VCC = 5 V
25
25
15
25
25
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns