M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 386
M306N4FGTFP
Manufacturer Part Number
M306N4FGTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N4FGGPU3.pdf
(94 pages)
3.M306N4FGGPU3.pdf
(414 pages)
Specifications of M306N4FGTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
23.11 CAN Module
Table 23.2 CAN Module Status Updating Period
(Example 1) Condition XIN 16 MHz CCLK: Divide-by-1
(Example 2) Condition XIN 16 MHz CCLK: Divide-by-2
(Example 3) Condition XIN 16 MHz CCLK: Divide-by-4
(Example 4) Condition XIN 16 MHz CCLK: Divide-by-8
(Example 5) Condition XIN 16 MHz CCLK: Divide-by-16
23.11.1 Reading CiSTR Register (i = 0, 1)
The CAN module on the M16C/6N Group (M16C/6N4) updates the status of the CiSTR register in a
certain period. When the CPU and the CAN module access to the CiSTR register at the same time, the
CPU has the access priority; the access from the CAN module is disabled. Consequently, when the
updating period of the CAN module matches the access period from the CPU, the status of the CAN
module cannot be updated. (See Figure 23.3 When Updating Period of CAN Module Matches Access
Period from CPU.)
Accordingly, be careful about the following points so that the access period from the CPU should not
match the updating period of the CAN module:
(a) There should be a wait time of 3fCAN or longer (see Table 23.2 CAN Module Status Updating
(b) When the CPU polls the CiSTR register, the polling period must be 3 fCAN or longer. (See Figure 23.5
3fCAN Period = 3
Period) before the CPU reads the CiSTR register. (See Figure 23.4 With Wait Time of 3 fCAN
before CPU Read.)
When Polling Period of CPU is 3 fCAN or Longer.)
Apr 14, 2006
page 362 of 376
✕
XIN (Original Oscillation Period)
✕
3 fCAN period = 3
3 fCAN period = 3
3 fCAN period = 3
3 fCAN period = 3
3 fCAN period = 3
Division Value of CAN Clock (CCLK)
✕
✕
✕
✕
✕
62.5 ns
62.5 ns
62.5 ns
62.5 ns
62.5 ns
✕
✕
✕
✕
✕
23. Usage Notes
1 = 187.5 ns
2 = 375 ns
4 = 750 ns
8 = 1.5 µs
16 = 3 µs
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