M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 84

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
8.1.3 On-chip Oscillator Clock
8.1.4 PLL Clock
This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock source
for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is 1 (on-chip
oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog
timer (refer to 11.1 Count Source Protective Mode).
After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register
to 1 (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function clocks,
in place of the main clock. If the main clock stops oscillating when the CM20 bit in the CM2 register is 1
(oscillation stop, re-oscillation detection function enabled) and the CM27 bit is 1 (oscillation stop,
re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the
necessary clock for the MCU.
The PLL clock is generated PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthesizer
is activated by setting the PLC07 bit to 1 (PLL operation). When the PLL clock is used as the clock source
for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the CM1
register to 1.
Before entering wait mode or stop mode, be sure to set the CM11 bit to 0 (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to 0
(PLL stops). Figure 8.11 shows the Procedure to Use PLL Clock as CPU Clock Source.
The PLL clock frequency is determined by the equation below. When the PLL clock frequency is 16 MHz
or more, set the PM20 bit in the PM2 register to 0 (2 waits).
NOTE:
Bits PLC02 to PLC00 can be set only once after reset. Table 8.2 shows an Example for Setting PLL Clock
Frequencies.
1. 24 MHz is available Normal-ver. only.
Apr 14, 2006
PLL clock frequency = f(XIN) ✕ (multiplying factor set by bits PLC02 to PLC00 in the PLC0 register)
page 60 of 376
(However, PLL clock frequency = 16 MHz, 20 MHz or 24 MHz
Table 8.2 Example for Setting PLL Clock Frequencies
NOTES:
(MHz)
XIN
10
12
1. PLL clock frequency = 16 MHz , 20 MHz or 24 MHz
2. 24 MHz is available Normal-ver. only.
3. Multiply by 6 is available Normal-ver. only.
8
4
5
6
4
PLC02
0
0
0
0
0
0
0
PLC01 PLC00
0
1
0
1
0
1
1
1
0
1
0
1
0
1
8. Clock Generation Circuit
Multiply
Factor
2
4
2
4
2
4
6
(3)
(1)
)
PLL Clock
(MHz)
24
16
20
(2)
(1)