HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 797

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.2.19 Transmit Interrupt Register (TRIMD)
TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back
completion for each frame using the TWB bit in EESR and an interrupt on transmit operations.
19.3
Using its direct memory access (DMA) function, the E-DMAC performs DMA transfer of
transmit/receive data between a Ethernet frame transmission/reception data storage destination of
user- specified (accessible memory space: transmit buffer/receive buffer) and the transmit/receive
FIFO in the E-DMAC. (The user cannot read and write data in the transmit/receive FIFO directly
via the CPU).
To enable the E-DMAC to perform DMA transfer, information (data) including a transmit/receive
data storage address and so forth, referred to as a descriptor, is required. Before Ethernet frame
transmission/reception, the E-DMAC reads descriptor information, then reads transmit data from
the transmit buffer or writes receive data to the receive buffer according to the read descriptor
information. By arranging multiple descriptors as a descriptor row (list) (to be placed in a
readable/writable memory space), multiple Ethernet frames can be transmitted or received
continuously.
Bit
31 to 1
0
Operation
Bit Name

TIS
Initial
Value
All 0
0
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transmit Interrupt Setting
0: Write-backed completion for each frame using the
1: Write-back completion for each frame is not
TWB bit in EESR is notified
notified
Rev. 1.00 Dec. 27, 2005 Page 753 of 932
REJ09B0269-0100