HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 673

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 17.11 SIOF Interrupt Sources
Whether an interrupt is issued or not as the result of an interrupt source is determined by the
SIIER settings. If an interrupt source is set to 1, and the corresponding bit in SIIER is set to 1, the
SIOF issues each interrupt.
Transmit/Receive Interrupt Flag: Transmit and receive interrupts are sent to the INTC or
DMAC by this interrupt flag based on the values of bits TDREQ and RDREQ in SISTR.
Table17.12 shows the setting condition of the transmit/receive interrupt flag.
No.
1
2
3
4
5
6
7
8
9
10
11
Classification
Transmission
(TXI)
Reception (RXI) RDREQ
Control (CCI)
Error (ERI)
Bit Name
TDREQ
TCRDY
RCRDY
TFEMP
RFFUL
TFUDR
TFOVR
RFOVR
RFUDR
FSERR
Function name
Transmit data transfer
request
Receive data transfer
request
Transmit control data
ready
Receive control data
ready
Transmit FIFO empty The transmit FIFO is empty.
Receive FIFO full
Transmit FIFO
underrun
Transmit FIFO
overrun
Receive FIFO
overrun
Receive FIFO
underrun
Frame
synchronization error
Rev. 1.00 Dec. 27, 2005 Page 629 of 932
Description
The number of transmit FIFO data
is equal to or less than the specified
value by transmit operation.
The receive FIFO stores data of
specified value or more.
The transmit control data register is
ready to be written.
The receive control data register
stores valid data.
The receive FIFO is full.
Serial data transmission timing has
arrived while the transmit FIFO is
empty.
Write to the transmit FIFO is
performed while the transmit FIFO
is full.
Serial data is received while the
receive FIFO is full.
The receive FIFO is read while the
receive FIFO is empty.
A synchronous signal is input
before the specified bit time has
been passed (in slave mode).
Section 17 Serial I/O with FIFO (SIOF)
REJ09B0269-0100