HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 778

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.5
RDLAR is a 32-bit readable/writable register that specifies the start address of the receive
descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length
indicated by the DL bit in EDMR. This register must not be written to during reception.
Modifications to this register should only be made while reception is disabled by the RR bit (= 0)
in the E-DMAC Receive Request Register (EDRRR).
19.2.6
EESR is a 32-bit readable/writable register that shows communications status information on the
E-DMAC in combination with the EtherC. The information in this register is reported in the form
of interrupt sources. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only
bit and not to be cleared by writing 1) and are not affected by writing 0. Each interrupt source can
also be masked by means of the corresponding bit in the EtherC/E-DMAC status interrupt
permission register (EESIPR).
The interrupts generated by this register are EINT0 for channel 0 and EINT1 for channel 1. For
interrupt priorities, see section 8, Interrupt Controller (INTC) and section 8.3.5, Interrupt
Exception Handling and Priority.
The EINT2 is an interrupt generated by the TSU_FNSR in the EtherC.
Rev. 1.00 Dec. 27, 2005 Page 734 of 932
REJ09B0269-0100
Bit
31 to 0
Bit
31
Receive Descriptor List Address Register (RDLAR)
EtherC/E-DMAC Status Register (EESR)
Bit Name
RDLA31 to
RDLA0
Bit Name

Initial
Value
All 0
Initial
Value
0
R/W
R/W
R/W
R
Description
Receive Descriptor Start Address
The lower bits are set as follows according to the
specified descriptor length.
16-byte boundary: RDLA3 and RDLA0 = 0000
32-byte boundary: RDLA4 and RDLA0 = 00000
64-byte boundary: RDLA5 and RDLA0 = 000000
Description
Reserved
This bit is always read as 0. The write value should
always be 0.