HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 773

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
• Receive missed-frame counter register (RMFCR0)
• Transmit FIFO threshold register (TFTR0)
• FIFO depth register (FDR0)
• Receiving method control register (RMCR0)
• E-DMAC operation control register (EDOCR0)
• Receive buffer write address register (RBWAR0)
• Receive descriptor fetch address register (RDFAR0)
• Transmit buffer read address register (TBRAR0)
• Transmit descriptor fetch address register (TDFAR0)
• Overflow alert FIFO threshold register (FCFTR0)
• Transmit interrupt register (TRIMD0)
Channel 1:
• E-DMAC mode register (EDMR1)
• E-DMAC transmit request register (EDTRR1)
• E-DMAC receive request register (EDRRR1)
• Transmit descriptor list address register (TDLAR1)
• Receive descriptor list address register (RDLAR1)
• EtherC/E-DMAC status register (EESR1)
• EtherC/E-DMAC status interrupt permission register (EESIPR1)
• Transmit/receive status copy enable register (TRSCER1)
• Receive missed-frame counter register (RMFCR1)
• Transmit FIFO threshold register (TFTR1)
• FIFO depth register (FDR1)
• Receiving method control register (RMCR1)
• E-DMAC operation control register (EDOCR1)
• Receive buffer write address register (RBWAR1)
• Receive descriptor fetch address register (RDFAR1)
• Transmit buffer read address register (TBRAR1)
• Transmit descriptor fetch address register (TDFAR1)
• Overflow alert FIFO threshold register (FCFTR1)
• Transmit interrupt register (TRIMD1)
Rev. 1.00 Dec. 27, 2005 Page 729 of 932
REJ09B0269-0100