HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 386

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 Bus State Controller (BSC)
12.4.1
CMNCR is a 32-bit register that controls the common items for each area. Do not access external
memory other than area 0 until the CMNCR initialization is complete.
Rev. 1.00 Dec. 27, 2005 Page 342 of 932
REJ09B0269-0100
Bit
31 to
15
14
13
12
11
Bit Name

BSD

MAP
BLOCK
Common Control Register (CMNCR)
Initial
Value
All 0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Bus Access Start Timing Specification After Bus
Acknowledge
Specifies the bus access start timing after the external bus
acknowledge signal is received.
0: Starts the external access at the same timing as the
1: Starts the external access one cycle following the
Reserved
This bit is always read as 0. The write value should always
be 0.
Space Specification
Selects the address map for the external address space.
The address maps to be selected are shown in tables 12.2
and 12.3.
0: Selects address map 1.
1: Selects address map 2.
Bus Lock Bit
Specifies whether or not the BREQ signal is received.
0: Receives BREQ.
1: Does not receive BREQ.
address drive start after the bus acknowledge signal is
received.
address drive start after the bus acknowledge signal is
received.